Abstract: A method for testing electronic devices, and to a test device that is, for test purposes, configured to be connected to an electronic system instead of an electronic device is disclosed. In one embodiment, the device includes at least one means for supplying a signal supplied by the electronic system and destined, in normal operation of the electronic system, for the electronic device, to a first electronic device that is configured to be connected to the device, and at least one further means for supplying a further signal supplied by the electronic system and destined, in normal operation of the electronic system, for the electronic device, to a second electronic device that is adapted to be connected to the device.

Abstract: A psuedostatic memory circuit is selected by a memory selection signal. A control circuit, in a first operating mode, carries out a refresh of the memory area at a refresh address after reception of the refresh request signal by generation of a refresh signal if the memory circuit is deselected or if, in the event of selection of the memory circuit by the memory selection signal, the access to the memory area is ended before the generation of a further refresh request signal. The control circuit, in a second operating mode, interrupts an access to the memory area for the writing and read-out of data and carries out a refresh of the memory area by generation of a refresh signal if the memory circuit is selected and a further refresh request signal is received before the ending of the access to the memory area.

Abstract: A method and a configuration for the output of bit error tables from semiconductor devices are described. A test control unit reads the bit error table from the memory device following a request from the test apparatus. Then, the bit error tables are transmitted sequentially to the test apparatus for further processing.

Abstract: A method and semiconductor circuit with which a self-test can be generated and tested with commands by which memory banks are interrogated simultaneously includes a processor for carrying out a built-in self-test and generating commands, each for testing only a respective single memory bank, and an additional processor connected downstream forms more complex multibank commands. Such multibank command formation enables a more diverse test of memories and is carried out faster. Principally, such multibank command generation using a combination of conventional single-bank commands has the advantage of not redeveloping a conventional BIST processor from scratch. It is necessary merely to connect a logic circuit downstream, with which conventional commands are combined, to form the multibank commands. As a result, complex self-test commands that simultaneously access a plurality of memory banks can be generated by a very low development outlay.

Abstract: A memory circuit, in particular a psuedostatic memory circuit, is selected by a memory selection signal. The memory circuit has memory areas and a control circuit in order to refresh a memory area of the memory circuit in accordance with a refresh request signal. The control circuit, in a first operating mode, carries out a refresh of the memory area at a refresh address after reception of the refresh request signal by generation of a refresh signal if the memory circuit is deselected or if, in the event of selection of the memory circuit by the memory selection signal, the access to the memory area is ended before the generation of a further refresh request signal. The control circuit, in a second operating mode, interrupts an access to the memory area for the writing and read-out of data and carries out a refresh of the memory area by generation of a refresh signal if the memory circuit is selected and a further refresh request signal is received before the ending of the access to the memory area.

Abstract: A method and a configuration for the output of bit error tables from semiconductor devices are described. A test control unit reads the bit error table from the memory device following a request from the test apparatus. Then, the bit error tables are transmitted sequentially to the test apparatus for further processing.

Abstract: A method and semiconductor circuit with which a self-test can be generated and tested with commands by which memory banks are interrogated simultaneously includes a processor for carrying out a built-in self-test and generating commands for testing only a respective single memory bank, and an additional processor connected downstream forms more complex multibank commands. Such multibank command formation enables a more diverse test of memories and is carried out faster. Principally, such multibank command generation using a combination of conventional single-bank commands has the advantage of not redeveloping a conventional BIST processor from scratch. It is necessary merely to connect a logic circuit downstream, with which conventional commands are combined, to form the multibank commands. As a result, complex self-test commands that simultaneously access a plurality of memory banks can be generated by a very low development outlay.