Abstract: A method for rapidly simulating combined analog circuits and digital circuits includes separating the combined circuits into a linear sub-network and logic sub-network. Shared nodes, shared by the linear sub-network and logic sub-network, are identified. The values of the shared nodes represent logic state values, or digital values, in the logic sub-network, and represent voltages, currents, control inputs and/or circuit parameters in the linear sub-network. Operation of the logic sub-network is simulated using logic node values for the shared nodes. Operation of the linear sub-network is simulated using linear node values for the shared nodes. The method allows fast simulation and rapid revision of mixed signal designs, saving design time and computing resources.