Abstract: The invention relates to a voltage converter comprising a rectification unit and a voltage regulation unit, wherein the input side of the voltage converter can have an AC voltage applied to it, the output side of the voltage converter can have a rectified voltage taken from it, and the voltage regulation unit regulates the power in the voltage converter.

Abstract: A circuit arrangement for voltage regulation including a first transistor coupled between a first node and a third node, a second transistor coupled between a second node and the third node, a third transistor coupled between the third node and an output node, and a control unit that can be coupled to the first transistor, that can be coupled to the second transistor, and is coupled to the third transistor, wherein the control unit is configured to steer the transistors such that a predetermined output voltage is provided at the output node when a supply voltage is provided at one of the first node and the second node.

Abstract: Device for supplying a data transfer unit with energy, having an energy supply input via which the energy can be fed into the data transfer unit, and a decoupling unit for coupling and decoupling the energy supply input to and from the data transfer unit, wherein the decoupling unit decouples when a supply voltage for the data transfer unit leaves a tolerance range.

Abstract: The invention relates to a voltage converter comprising a rectification unit and a voltage regulation unit, wherein the input side of the voltage converter can have an AC voltage applied to it, the output side of the voltage converter can have a rectified voltage taken from it, and the voltage regulation unit regulates the power in the voltage converter.

Abstract: A voltage supply circuit has a first supply voltage input connected to a first comparator and to a first voltage regulator, the first comparator controlling the first voltage regulator. A second supply voltage input is connected to a second comparator and to a second voltage regulator, the second comparator controlling the second voltage regulator. A supply voltage output is connected to the outputs of the two voltage regulators and is fed back to the two comparators.

Abstract: Circuit for generating a supply voltage having a voltage input connected to a voltage regulator that generates a first supply voltage and to a low-noise voltage regulator that generates a low-noise supply voltage. A control unit determines which of the two supply voltages is switched to a supply voltage output of the circuit.

Abstract: A circuit arrangement for voltage regulation including a first transistor coupled between a first node and a third node, a second transistor coupled between a second node and the third node, a third transistor coupled between the third node and an output node, and a control unit that can be coupled to the first transistor, that can be coupled to the second transistor, and is coupled to the third transistor, wherein the control unit is configured to steer the transistors such that a predetermined output voltage is provided at the output node when a supply voltage is provided at one of the first node and the second node.

Abstract: A selection circuit having a comparator with comparator inputs connected to first and second voltage inputs), respectively, and a comparator output connected to a control input of a first controllable switch and an inverter. The selection circuit also has a second controllable switch having a second control input connected to the inverter. The first voltage input is connectable to a selection circuit output by the first controllable switch and the second voltage input is connectable to the selection circuit output by the second controllable switch. The inverter has a power supply connector connected to the first voltage input and the comparator has a power supply connector connected to the second voltage input.

Abstract: Memory sense amplifier unit for amplifying a data signal read from a memory via bit lines (2, 3), having a precharge circuit (4) comprising PMOS transistors (5, 6) and serving for rapidly precharging the bit lines (2, 3) to a supply voltage potential (VDD) of the sense amplifier unit (1); a first amplifier stage (43) comprising feedback NMOS transistors (21, 22, 24, 26) and serving for voltage level shifting and for amplifying the data signal present on the bit lines (2, 3); and having a second amplifier stage (66) for amplifying further the signal output by the first amplifier stage (43), in which case the first amplifier stage (43) can be initialized to the supply voltage potential (VDD) and the second amplifier stage (43) can be initialized to ground potential (VSS).

Abstract: Memory sense amplifier unit for amplifying a data signal read from a memory via bit lines (2, 3), having a precharge circuit (4) comprising PMOS transistors (5, 6) and serving for rapidly precharging the bit lines (2, 3) to a supply voltage potential (VDD) of the sense amplifier unit (1); a first amplifier stage (43) comprising feedback NMOS transistors (21, 22, 24, 26) and serving for voltage level shifting and for amplifying the data signal present on the bit lines (2, 3); and having a second amplifier stage (66) for amplifying further the signal output by the first amplifier stage (43), in which case the first amplifier stage (43) can be initialized to the supply voltage potential (VDD) and the second amplifier stage (43) can be initialized to ground potential (VSS).