Abstract: A clock generation system includes an oscillator and one or more clock generators. The oscillator provides inphase and quadrature oscillator signals having a fixed frequency. Each clock generator receives the oscillator signals and generates a respective output clock signal. Within each clock generator, two weight generators receive two sequences of phase values and generate weights for two analog signals. Two signal generators multiply the inphase and quadrature oscillator signals with the weights from the two weight generators and provide the two analog signals having leading edges determined by the two sequences of phase values. A digital clock generator generates a DCLK signal based on the two analog signals. A divider divides the DCLK signal by N in frequency and provides the output clock signal. A phase generator generates the two sequences of phase values for the two analog signals based on a frequency control value and a phase offset value.

Abstract: A network switch having a shared memory architecture for storing data frames has a set of programmable thresholds that specify when flow control should be initiated on a selected network port. The network switch includes a queue for storing free frame pointers, each specifying available memory locations in an external memory for storing data frames received from a network station. The network switch takes a frame pointer from a free buffer queue for each received data frame, and stores the received data frame in the location in external memory specified by the frame pointer while a decision making engine within the switch determines the appropriate destination ports.

Abstract: A network having a shared memory architecture for storing data frames has a set of programmable thresholds that specify when flow control should be initiated on full-duplex network ports. The network switch includes a queue for storing free frame pointers that specify available memory locations in an external memory for storing data frames received from a network station. The network switch takes a frame pointer from a free buffer queue for each received data frame, and stores the received data frame in the location in external memory specified by the frame pointer while a decision making engine within the switch determines the appropriate destination ports. Flow control is initiated based on the number of available frame pointers by transmitting a PAUSE frame having a selected PAUSE interval to a transmitting network station.

Abstract: An arrangement in a processor circuit for concurrently executing a plurality of instructions. An instruction control unit concurrently supplies a plurality of instruction addresses to an instruction memory. Each clock cycle, the instruction memory receives one instruction address from the instruction control unit based on a count value and selectively fetches and outputs corresponding to the received instruction address. An instruction decoder decodes, each clock cycle, the instruction output from the instruction memory the preceding clock cycle while identifying a memory address and an instruction operation for each fetched instruction. A memory interface, based on the count value, selectively supplies to an external memory, each clock cycle, one of the supplied memory addresses and identified by the instruction decoder for the respective fetched instructions.

Abstract: An integrated multiport switch (IMS) in which an on-chip management information base (MIB) accumulation processor enables monitoring of a significantly larger number of MIB objects to be stored in external memory while minimizing media access controller (MAC) complexity. A MAC for each port in the IMS outputs a MIB report for each transmission or reception of data according to a specific encoded format to a MIB engine. The MIB engine decodes the MIB report into a plurality of associated MIB objects, which are temporarily accumulated until the external memory is updated. The MIB engine initiates the stored MIB value updating process by retrieving the values from the external memory and adding the accumulated MIB objects to the retrieved values. The updated MIB objects are then transmitted back to the external memory for storage therein and the MIB engine object values are reset.

Abstract: The present invention comprises a system and method for reducing the pin count between a plurality of MAC and PHY devices within a switching element. In this embodiment, the switching element includes a plurality of general serial interfaces for providing connections between respective MAC and PHY devices and each of the plurality of general serial interfaces operates at a first data rate. The system and method comprises a multiplexer coupled to the plurality of general serial interfaces and a pad member including a plurality of pins. The pad member is coupled to the multiplexer and receives multiplexed signals from the plurality of general serial interfaces. The multiplexer operates at a second data rate that is a multiple of the first data rate. Generally, a system and method in accordance with the present invention allows for the multiplexing of a general purpose serial interface (GPSI) to reduce the pin count in some cases by as much as 75% and also synchronize the MAC/PHY interface.

Abstract: A random access memory (RAM) having a prescribed number of bits defining a word length includes memory cells that enable selective overwriting on a bit-by-bit basis. Each memory cell includes a logic gate for generating a gating signal in response to a supplied write signal and a bit enable signal. The gating signal selectively connects the bistable latch of the memory cell to a voltage source to enable storage of the supplied data bit. Hence, selected bits can be written to an address word, without overwriting the unselected bits in the stored word, by supplying a mask signal that selectively drives the logic gates of the selected bits. The mask signal can also be used to configure a RAM as a dynamic-width memory, enabling use of the RAM for variable-width storage applications without the necessity of external decoding logic.

Abstract: A random access memory (RAM) having a prescribed number of bits defining a word length includes memory cells that enable selective overwriting on a bit-by-bit basis. Each memory cell includes a logic gate for generating a gating signal in response to a supplied write signal and a bit enable signal. The gating signal selectively connects the bistable latch of the memory cell to a voltage source to enable storage of the supplied data bit. Hence, selected bits can be written to an address word, without overwriting the unselected bits in the stored word, by supplying a mask signal that selectively drives the logic gates of the selected bits. The mask signal can also be used to configure a RAM as a dynamic-width memory, enabling use of the RAM for variable-width storage applications without the necessity of external decoding logic.

Abstract: A digital to analog converter that includes circuitry that converts sequences of positive and negative digital data samples into electrical currents and current mirror circuitry that generates an analog waveform by combining and amplifying the electrical currents.

Abstract: A digital phase lock loop and system for data extraction and clock recovery of Ethernet data reduces power consumption, area, and noise sensitivity. In one aspect, a digital phase lock loop (PLL) includes a data extraction and end of transmission delimiter (ETD) circuit, an edge detection comparator coupled to the data extraction and ETD circuit, an up/down counter coupled to the edge detection comparator, and a phase adjustment oscillator coupled to the counter and to the data extraction and ETD circuit for producing phase adjustments in a reference clock signal in accordance with shifts in the frequency of the data. In a system aspect of the present invention, the system receives the data in a digital PLL circuit, and adjusts a phase of a reference clock and a sample clock to track transitions in the data through the digital PLL.

Abstract: A system for synthesizing a waveform that employs combinatorial logic to generate digital data for each of a set of preselected waveform. The system includes circuitry for selecting a sequence of the preselected waveform pulses in response to a data signal and circuitry for converting the digital data for the sequence of the preselected waveform pulses into the waveform.

Abstract: N separate identical finite state machines service N corresponding channels. In one embodiment, each channel operating at a clock frequency F is serviced by the same combinatorial logic block which runs at an N*F clock frequency. The channel inputs are delivered to the shared combinatorial logic block via an N-to-1 multiplexor. N separate output registers continuously provide output to the N separate channels. Each output register is loaded every Nth clock cycle. Although the combinatorial logic is shared amongst multiple machines, the state variables for each machine must be stored in a memory unit. In an embodiment of the memory unit, N separate state variable registers are loaded using the same load enable control signals as are used for the N output registers. The current state for the appropriate channel is selected by means of an N-to-1 multiplexor. An N-element shift register sequentially provides the appropriate channel's state variables to the shared combinatorial logic block.

Abstract: An ATM switch is provided with two stages of crossbar switches with internal blocking paths between the stages. To define priorities of input ports, switches of stage 1 calculate the effective serial numbers of the input ports based on their physical serial numbers and global offset values. To provide dynamic modification of the input port priorities, the global offset values can be changed in each cell cycle of the ATM switch. A sequence of encoded requests for access to required output ports are sent from each switch of stage 1 to each switch of stage 2. Contention arbitration logic in each switch of stage 2 determines which requests may be granted so as to avoid blocking paths between stages 1 and 2, and to prevent out-of-order cell delivery. Signals that acknowledge acceptance of cells and provide information required to establish the serial numbers of the accepted input ports are sent back from each switch of stage 2 to each switch of stage 1.

Abstract: A digital to analog converter that includes circuitry that converts sequences of positive and negative digital data samples into electrical currents and current mirror circuitry that generates an analog waveform by combining and amplifying the electrical currents.

Abstract: A system for synthesizing a waveform includes waveform synthesis circuitry that generates digital data for each of a set of waveform pulses having preselected slopes at zero-crossing. A sequencer tracks the history of information contained in a data signal and selects a sequence of the waveform pulses in response to the history such that the sequence conveys the history of information while minimizing mismatches between the slopes of adjacent waveform pulses in the sequence.

Abstract: An ATM switch with multicast capability uses a feedback mechanism for resolving contentions. A multicast network reads N cells from an input queue, replicates multicast cells and translates their addresses in accordance with an external look-up table. The processed N cells are stored in a temporary buffer until information regarding the number (F) of cells fed back due to contention in the previous switching cycle is available. A rotator positions N-F cells from the temporary buffer on inputs of an output network so as to assign the cells from the temporary buffer a lower priority than a priority of the feed back cells. The output network selects the cells that can be switched to their destinations and transfers them to output ports. The cells that cannot be switched due to contention are fed back to be presented for the output network consideration in the next switching cycle.