Abstract: A system for network data transactions, the system including an ingress port to receive data frames and timestamp received data frames, a frame analyzer to forward the data frames to a processor, the processor to extract timing information from the data frames and update the data frames based on updated timing calculations and output updated data frames via one or more egress ports. Data frames are timestamped at ingress and egress ports, and egress timestamps are saved in a timestamp memory. The system reduces overall network delays by using dedicated hardware and stored timestamp information.

Abstract: A system for network data transactions, the system including an ingress port to receive data frames and timestamp received data frames, a frame analyzer to forward the data frames to a processor, the processor to extract timing information from the data frames and update the data frames based on updated timing calculations and output updated data frames via one or more egress ports. Data frames are timestamped at ingress and egress ports, and egress timestamps are saved in a timestamp memory. The system reduces overall network delays by using dedicated hardware and stored timestamp information.

Abstract: A PHY chip for a synchronous Ethernet system includes N network input/output (I/O) ports, a first external recovered clock input, a first recovered clock output, and a first clock multiplexer having a plurality of data inputs, a select input, and an output coupled to the first recovered clock output, at least one of the data inputs coupled to a first recovered clock from a respective one of the N network I/O ports, a first additional data input coupled to the first external recovered clock input.

Abstract: A PHY chip for a synchronous Ethernet system includes N network input/output (I/O) ports, a first external recovered clock input, a first recovered clock output, and a first clock multiplexer having a plurality of data inputs, a select input, and an output coupled to the first recovered clock output, at least one of the data inputs coupled to a first recovered clock from a respective one of the N network I/O ports, a first additional data input coupled to the first external recovered clock input.

Abstract: A PHY constituted of: a clock arranged to generate a time signal indicative of the current time; and an egress stamp functionality arranged to: receive a data packet on the egress side, extract data from a predetermined section of the received data packet, and responsive to the extracted data, perform one of a plurality of predetermined timestamp operations, the plurality of predetermined timestamp operations comprising: generating a timestamp signal responsive to the generated time signal; not generating a timestamp signal; or modifying a timestamp written in the received data packet.

Abstract: A phase predictor to accurately detect and predict the phase relationship between two clocks running at different frequencies. The phase relationship can be used to record the transmission and reception times of Ethernet frames transmitted over a transmission medium with very high accuracy.

Abstract: A phase predictor to accurately detect and predict the phase relationship between two clocks running at different frequencies. The phase relationship can be used to record the transmission and reception times of Ethernet frames transmitted over a transmission medium with very high accuracy.

Abstract: A transparent clock converter is interposed between a non-precision time protocol (non-PTP) enabled network node and other portions of the network. The transparent clock converter effectively converts the non-PTP node into a transparent clock node. In some embodiments the transparent clock converter includes physical layer devices, but not media access controllers.

Abstract: A PHY constituted of: a clock arranged to generate a time signal indicative of the current time; and an egress stamp functionality arranged to: receive a data packet on the egress side, extract data from a predetermined section of the received data packet, and responsive to the extracted data, perform one of a plurality of predetermined timestamp operations, the plurality of predetermined timestamp operations comprising: generating a timestamp signal responsive to the generated time signal; not generating a timestamp signal; or modifying a timestamp written in the received data packet.

Abstract: A transparent clock converter is interposed between a non-precision time protocol (non-PTP) enabled network node and other portions of the network. The transparent clock converter effectively converts the non-PTP node into a transparent clock node. In some embodiments the transparent clock converter includes physical layer devices, but not media access controllers.

Abstract: A transparent clock converter is interposed between a non-precision time protocol (non-PTP) enabled network node and other portions of the network. The transparent clock converter effectively converts the non-PTP node into a transparent clock node. In some embodiments the transparent clock converter includes physical layer devices, but not media access controllers.

Abstract: An advanced power strip includes a housing having at least one control outlet, at least one switched outlet, and at least one auxiliary input port; and at least one auxiliary device coupled to the at least one auxiliary input port. The advanced power strip can be configured to a) allow for master/slave control sensing the current produced by a control device coupled to the at least one control outlet, and, if current is detected, allowing current to be drawn by any device coupled to the at least one switched outlet; and b) allow for manual control of the switched outlets via the at least one auxiliary device coupled to the at least one auxiliary input port.

Abstract: A transparent clock converter is interposed between a non-precision time protocol (non-PTP) enabled network node and other portions of the network. The transparent clock converter effectively converts the non-PTP node into a transparent clock node. In some embodiments the transparent clock converter includes physical layer devices, but not media access controllers.