Patents by Inventor Thomas John Aton
Thomas John Aton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9343332Abstract: A method of aligning a new pattern to more than one previously defined pattern during the manufacture of an integrated circuit. A method of aligning a photolighography pattern reticle to a first previously defined pattern in a first direction and also aligning the photolithography pattern reticle to a second previously defined pattern in a second direction. A method of aligning a photolighography pattern reticle to two previously defined patterns in the same direction.Type: GrantFiled: July 20, 2015Date of Patent: May 17, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Thomas John Aton, Steven Lee Prins, Scott William Jessen
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Publication number: 20150325472Abstract: A method of aligning a new pattern to more than one previously defined pattern during the manufacture of an integrated circuit. A method of aligning a photolighography pattern reticle to a first previously defined pattern in a first direction and also aligning the photolithography pattern reticle to a second previously defined pattern in a second direction. A method of aligning a photolighography pattern reticle to two previously defined patterns in the same direction.Type: ApplicationFiled: July 20, 2015Publication date: November 12, 2015Inventors: Thomas John ATON, Steven Lee PRINS, Scott William JESSEN
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Patent number: 9117775Abstract: A method of aligning a new pattern to more than one previously defined pattern during the manufacture of an integrated circuit. A method of aligning a photolighography pattern reticle to a first previously defined pattern in a first direction and also aligning the photolithography pattern reticle to a second previously defined pattern in a second direction. A method of aligning a photolighography pattern reticle to two previously defined patterns in the same direction.Type: GrantFiled: May 24, 2012Date of Patent: August 25, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Thomas John Aton, Steven Lee Prins, Scott William Jessen
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Patent number: 8446175Abstract: An integrated circuit containing CMOS logic gates and a logic-cell-compatible decoupling capacitor adjacent to the logic gates, in which the decoupling capacitor includes p+/n and n+/p capacitors, resistors between 1 and 1000 ohms connecting the capacitors to Vdd and Vss buses, and gate elements which have widths and spacings similar to the adjacent logic gates. A process of forming an integrated circuit containing CMOS logic gates and a logic-cell-compatible decoupling capacitor adjacent to the logic gates, in which the decoupling capacitor includes p+/n and n+/p capacitors, resistors between 1 and 1000 ohms connecting the capacitors to Vdd and Vss buses, and gate elements which have widths and spacings similar to the adjacent logic gates.Type: GrantFiled: February 22, 2011Date of Patent: May 21, 2013Assignee: Texas Instruments IncorporatedInventor: Thomas John Aton
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Publication number: 20120302059Abstract: A method of aligning a new pattern to more than one previously defined pattern during the manufacture of an integrated circuit. A method of aligning a photolighography pattern reticle to a first previously defined pattern in a first direction and also aligning the photolithography pattern reticle to a second previously defined pattern in a second direction. A method of aligning a photolighography pattern reticle to two previously defined patterns in the same direction.Type: ApplicationFiled: May 24, 2012Publication date: November 29, 2012Applicant: Texas Instruments IncorporatedInventors: Thomas John ATON, Steven Lee PRINS, Scott William JESSEN
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Publication number: 20110148466Abstract: An integrated circuit containing CMOS logic gates and a logic-cell-compatible decoupling capacitor adjacent to the logic gates, in which the decoupling capacitor includes p+/n and n+/p capacitors, resistors between 1 and 1000 ohms connecting the capacitors to Vdd and Vss buses, and gate elements which have widths and spacings similar to the adjacent logic gates. A process of forming an integrated circuit containing CMOS logic gates and a logic-cell-compatible decoupling capacitor adjacent to the logic gates, in which the decoupling capacitor includes p+/n and n+/p capacitors, resistors between 1 and 1000 ohms connecting the capacitors to Vdd and Vss buses, and gate elements which have widths and spacings similar to the adjacent logic gates.Type: ApplicationFiled: February 22, 2011Publication date: June 23, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Thomas John Aton
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Patent number: 7927782Abstract: One embodiment of the present invention relates to a method for which a two mask lithography process can be used to reduce design density. The two mask process uses a first mask to expose a first photoresist layer located above a hard mask layer. The first photoresist is exposed in such a way that the level forms one or more lines, on opposite sides of a cell boundary. The hard mask is then etched. A second photoresist layer is deposited above the hard mask. The second mask is used to expose the second photoresist layer in such a way that a space is formed along the cell boundary equal to the minimum space of the level as required by the design rules. The hard mask is then etched again. The hard mask is subsequently used to pattern the layer below it. Other methods and structures are also disclosed.Type: GrantFiled: December 28, 2007Date of Patent: April 19, 2011Assignee: Texas Instruments IncorporatedInventor: Thomas John Aton
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Publication number: 20090169832Abstract: One embodiment of the present invention relates to a method for which a two mask lithography process can be used to reduce design density. The two mask process uses a first mask to expose a first photoresist layer located above a hard mask layer. The first photoresist is exposed in such a way that the level forms one or more lines, on opposite sides of a cell boundary. The hard mask is then etched. A second photoresist layer is deposited above the hard mask. The second mask is used to expose the second photoresist layer in such a way that a space is formed along the cell boundary equal to the minimum space of the level as required by the design rules. The hard mask is then etched again. The hard mask is subsequently used to pattern the layer below it. Other methods and structures are also disclosed.Type: ApplicationFiled: December 28, 2007Publication date: July 2, 2009Inventor: Thomas John Aton
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Patent number: 6208151Abstract: The improved method for microscopic measurement of electrical characteristics comprises a standard atomic force microscope (AFM). The AFM includes a pointed, conductively coated tip attached to one end of a softly compliant cantilever arm, also capable of conducting electricity. The other end of the cantilever arm is attached to the top of a piezo-electric z-axis driver which will raise and lower the cantilever arm as the AFM tip is scanned across the surface of a sample. A piezo-electric X-Y scanstage controller may also be provided and connected to the bottom of the z-axis driver. The X-Y scanstage is preferably capable of scanning the movement of the entire system including the Z-axis driver, cantilever arm and AFM tip.Type: GrantFiled: December 18, 1998Date of Patent: March 27, 2001Assignee: Texas Instruments IncorporatedInventors: Thomas John Aton, Leigh Ann Files