Patents by Inventor Thomas John Francis

Thomas John Francis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7531896
    Abstract: A system and method is disclosed for minimizing increases in via resistance by applying a nitrogen plasma after a titanium liner deposition. A via in a semiconductor device is formed by placing a metal layer on a substrate and placing a layer of anti-reflective coating (ARC) titanium nitride (TiN) over the metal layer. A layer of dielectric material is placed over the ARC TiN layer and a via passage is etched through the dielectric and partially through the ARC TiN layer. A titanium layer is then deposited and subjected to a nitrogen plasma process. The nitrogen plasma converts the titanium layer to a first layer of titanium nitride. The first layer of titanium nitride does not react with fluorine to form a high resistance compound. Therefore the electrical resistance of the first layer of titanium nitride does not significantly increase during subsequent thermal cycles.
    Type: Grant
    Filed: September 1, 2006
    Date of Patent: May 12, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Sergei Drizlikh, Thomas John Francis
  • Patent number: 7504340
    Abstract: A system and method is disclosed for providing contact etch selectivity for the etching of a plurality of contact etch holes through a dielectric layer of an integrated circuit. The method comprises the steps of obtaining a value of the reactive ion etch (RIE) lag for the dielectric layer, and selecting different values for the diameters of the contact etch holes based upon the desired depths of the contact etch holes and on the value of the RIE lag for the dielectric layer. The invention also comprises a contact diameter application processor that is capable of using RIE lag data to calculate contact diameters for contact etch holes for a mask design layout of an integrated circuit.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: March 17, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Sergei Drizlikh, Thomas John Francis, Lee James Jacobson
  • Patent number: 7101787
    Abstract: A system and method is disclosed for minimizing increases in via resistance by applying a nitrogen plasma after a titanium liner deposition. A via in a semiconductor device is formed by placing a metal layer on a substrate and placing a layer of anti-reflective coating (ARC) titanium nitride (TiN) over the metal layer. A layer of dielectric material is placed over the ARC TiN layer and a via passage is etched through the dielectric and partially through the ARC TiN layer. A titanium layer is then deposited and subjected to a nitrogen plasma process. The nitrogen plasma converts the titanium layer to a first layer of titanium nitride. The first layer of titanium nitride does not react with fluorine to form a high resistance compound. Therefore the electrical resistance of the first layer of titanium nitride does not significantly increase during subsequent thermal cycles.
    Type: Grant
    Filed: April 9, 2004
    Date of Patent: September 5, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Sergei Drizlikh, Thomas John Francis