Patents by Inventor Thomas John Hartswick

Thomas John Hartswick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5723898
    Abstract: The present disclosure sets forth an improved integrated circuit in which circuit elements, adjacent to a fuse, are protected by barriers positioned adjacent the fuse. In the improved integrated circuit the barriers are non-frangible, high melting point structures buried in the passivating layer, covering a wiring layer containing a fuse, and are between the fuse and adjacent circuit elements in the wiring layer structures. Also taught is a method of protecting circuit elements adjacent a fuse comprising the steps of depositing an insulating layer on the surface of a semiconductor device having active regions therein, forming a plurality of fuses and circuit elements in said layer, coating said fuses and elements with a second insulating layer, patterning said second insulating layer to form grooves between each of said fuses and any adjacent fuse or circuit element, and depositing a high melting point and non-frangible material in said grooves.
    Type: Grant
    Filed: October 4, 1996
    Date of Patent: March 3, 1998
    Assignee: International Business Machines Corp.
    Inventors: Richard Alfred Gilmour, Thomas John Hartswick, David Charles Thomas, Ronald Robert Uttecht, Erick Gregory Walton