Abstract: A circuit arrangement and method detect external requests to access a memory array in a hardware simulation accelerator during performance of a simulation on a simulation model and access the memory array without halting the simulation in response to detecting the external request. Such functionality may be provided, for example, by detecting such external requests in response to processing a predetermined instruction in an instruction stream associated with the simulation model, where the predetermined instruction is configured to ensure a predetermined period of inactivity for the memory array. By doing so, the memory array can be accessed from outside of the hardware simulation accelerator during the processing of a simulation, and without requiring that the simulation be halted, thus reducing overhead and improving simulation efficiency.

Abstract: A hardware simulation accelerator to simulate logic designs, a method to encode instructions for use in the hardware simulation accelerator, and a computer program product having code of the method by which the hardware simulation accelerator can read encoded instructions to simulate the logic design, and computer program product of the encoded instructions to simulate a logic design in a hardware accelerator. Each instruction has one of a plurality of opcodes, the opcodes select which of the hardware resources of the hardware simulation accelerator will implement and use the values set forth in other programmable bits of the encoded instruction. The encoded instruction may be a routing and/or a gate evaluation instruction.

Abstract: A hardware simulation accelerator to simulate logic designs, a method to encode instructions for use in the hardware simulation accelerator, and a computer program product having code of the method by which the hardware simulation accelerator can read encoded instructions to simulate the logic design, and computer program product of the encoded instructions to simulate a logic design in a hardware accelerator. Each instruction has one of a plurality of opcodes, the opcodes select which of the hardware resources of the hardware simulation accelerator will implement and use the values set forth in other programmable bits of the encoded instruction. The encoded instruction may be a routing and/or a gate evaluation instruction.