Abstract: A method for forming a memory device includes: providing a substrate including at least word line structures and active regions, and a bottom dielectric layer and bit line contact layers that are on a top surface of the substrate; part of the bit line contact layers are etched to form bit line contact layers at different heights; conducting layers are formed, top surfaces of the conducting layers being at different heights in a direction perpendicular to an extension direction of the word line structure, and the top surfaces of the conducting layers being at different heights in the extension direction of the word line structure; top dielectric layers are formed; and etching is performed to form separate bit line structures.

Abstract: The present disclosure provides a forming method of a memory and a memory. The method includes: providing a substrate, wherein the substrate includes at least word line structures and active areas, and a bottom dielectric layer and a bit line contact layer located on a top surface of the substrate, the bottom dielectric layer has bit line contact openings, the bit line contact openings expose the active areas in the substrate, and the bit line contact layer covers the bottom dielectric layer and fills the bit line contact openings; etching parts of the bit line contact layer, and forming first bit line contact layer with different heights; forming a conductive layer, a top surface of the conductive layer is located at different heights in a direction perpendicular to an extension direction of the word line structures.

Abstract: A substrate processing device includes a substrate support portion supporting a substrate, a fluid supply portion arranged above the substrate support portion and configured to supply an initiator and a monomer toward the substrate, and a laser generation portion configured to irradiate a laser in a direction intersecting a direction in which the initiator and the monomer are supplied and parallel to a surface of the substrate, wherein the initiator and the monomer are polymerized by the laser and deposited on the substrate.

Abstract: Provided is a substrate treatment apparatus using a supercritical fluid, the apparatus capable of depositing a conformal film in a trench with a high aspect ratio and capable of performing void-free complete gap-filling. The substrate treatment apparatus includes: an upper vessel including a first body and a supply port formed in the first body and supplying a process fluid; a baffle plate installed in the upper vessel and supplying the process fluid supplied through the supply port to a treatment space by diffusing the process fluid; a lower vessel including a second body and an exhaust port formed in the second body and exhausting the process fluid from the treatment space; and a support plate installed in the lower vessel to face the baffle plate and supporting a substrate, wherein while a supercritical process is performed in the treatment space, the support plate is heated so that the temperature of the support plate is higher than that of the first body.

Abstract: A substrate processing method using a supercritical fluid is provided that can deposit a conformal film in a trench with a high aspect ratio and allows complete filling without voids.

Abstract: A substrate processing method using a supercritical fluid is provided that can deposit a conformal film in a trench with a high aspect ratio and allows complete filling without voids. The substrate processing method comprises supplying a first process fluid containing a precursor and a first supercritical fluid to a reactor to raise a pressure of the reactor to a first pressure equal to or greater than a critical pressure, subsequently, first venting the reactor to lower the pressure in the reactor to a second pressure, subsequently, supplying a second process fluid containing a reducing fluid to the reactor to raise the pressure in the reactor to a third pressure, subsequently, second venting the reactor to lower the pressure in the reactor to a fourth pressure.

Abstract: A method of fabricating a semiconductor device, which is capable of sufficiently filling trenches, is provided. The method includes: providing a substrate having defined thereon a plurality of active regions, which are spaced apart from one another by a device isolation film; forming a plurality of wordline trenches, which extend longitudinally in one direction, by removing portions of the active regions and portions of the device isolation film; forming gate insulating films along inner sidewalls of the wordline trenches; and forming wordlines, which fill portions of the wordline trenches, on the gate insulating films, wherein the forming the wordlines, comprises filling the portions of the wordline trenches with metal layers using a supercritical fluid deposition (SFD) method.

Abstract: A semiconductor device including memory cells that are three-dimensionally arranged is provided.

Abstract: A method of forming a semiconductor device includes pretreating a semiconductor substrate including at least one buried power rail for power transmission, based on chemical reaction by supplying a pretreatment gas for surface treatment onto a backside of the semiconductor substrate, forming at least one metal catalyst layer on the backside of the semiconductor substrate so as to be at least partially aligned with the at least one buried power rail, and forming at least one backside via hole by supplying an etchant to the semiconductor substrate to anisotropically etch the semiconductor substrate between the at least one metal catalyst layer and the at least one buried power rail while the at least one metal catalyst layer is descending into the semiconductor substrate by using metal assisted chemical etching (MACE).

Abstract: Provided is a method of manufacturing a semiconductor device, the method including steps of providing a semiconductor substrate having one or more trenches, forming a gate insulating layer on the semiconductor substrate inside the trenches, and forming a buried gate electrode layer on the gate insulating layer to at least partially fill the trenches, wherein the step of forming the buried gate electrode layer includes a step of repeating a unit cycle a plurality of times, the unit cycle including an atomic layer deposition (ALD) process for forming a conductive layer on the gate insulating layer to serve as the buried gate electrode layer, and an atomic layer etching (ALE) process for preferentially etching portions of the conductive layer formed near the trenches and portions of the conductive layer formed on upper ends of the trenches over other portions of the conductive layer inside the trenches.

Abstract: A semiconductor device includes bit lines each extending in a first direction on a substrate and spaced apart from each other in a second direction, semiconductor patterns disposed on each of the bit lines and including a first semiconductor pattern disposed on a first bit line, and a second semiconductor pattern arranged to be offset in the second direction from the first semiconductor pattern on the first bit line, word lines each extending in the second direction and surrounding a sidewall of each of the semiconductor patterns, the word lines including a first word line extending in the second direction and surrounding the first semiconductor pattern, and a second word line spaced apart in the first direction from the first word line and extending in the second direction while surrounding the second semiconductor pattern, and storage nodes respectively disposed on the semiconductor patterns.

Abstract: An annealing system is provided that includes a chamber body that defines a chamber, a support to hold a workpiece and a robot to insert the workpiece into the chamber. The annealing system also includes a first gas supply to provide a hydrogen gas, a pressure source coupled to the chamber to raise a pressure in the chamber to at least 5 atmospheres, and a controller configured to cause the robot to transport a workpiece having a metal film thereon into the chamber, where the metal film contains fluorine on a surface or embedded within the metal film, to cause the first gas supply to supply the hydrogen gas to the chamber and form atomic hydrogen therein, and to cause the pressure source to raise a pressure in the chamber to at least 5 atmospheres while the workpiece is held on the support in the chamber.

Abstract: An annealing system is provided that includes a chamber body that defines a chamber, a support to hold a workpiece and a robot to insert the workpiece into the chamber. The annealing system also includes a first gas supply to provide a hydrogen gas, a pressure source coupled to the chamber to raise a pressure in the chamber to at least 5 atmospheres, and a controller configured to cause the robot to transport a workpiece having a metal film thereon into the chamber, where the metal film contains fluorine on a surface or embedded within the metal film, to cause the first gas supply to supply the hydrogen gas to the chamber and form atomic hydrogen therein, and to cause the pressure source to raise a pressure in the chamber to at least 5 atmospheres while the workpiece is held on the support in the chamber.

Abstract: The present disclosure provides a forming method of a memory and a memory. The method includes: providing a substrate, wherein the substrate includes at least word line structures and active areas, and a bottom dielectric layer and a bit line contact layer located on a top surface of the substrate, the bottom dielectric layer has bit line contact openings, the bit line contact openings expose the active areas in the substrate, and the bit line contact layer covers the bottom dielectric layer and fills the bit line contact openings; etching parts of the bit line contact layer, and forming first bit line contact layer with different heights; forming a conductive layer, a top surface of the conductive layer is located at different heights in a direction perpendicular to an extension direction of the word line structures.

Abstract: Some embodiments of the present application provide a memory forming method and a memory. The method includes: providing a substrate including at least word line structures and active regions, and bottom dielectric layers and bit line contact layers located on a top surface of the substrate, the bottom dielectric layer having bit line contact openings exposing the active regions in the substrate, and the bit line contact layers covering the bottom dielectric layers and filling the bit line contact openings; etching part of the bit line contact layers to form the bit line contact layers of different heights; forming conductive layers, top surfaces of the conductive layers being at the same height in a direction perpendicular to an extension direction of the word line structures; and the top surfaces of the conductive layers being at different heights in the extension direction of the word line structures; forming top dielectric layers.

Abstract: The present disclosure generally relate to thin films incorporating high aspect ratio feature definitions and methods for forming the same. As gate height increases, 3D NAND gate stacks are subject to higher aspect ratio etching. Due to the current limitations of etching techniques, the vertical etch profile typically tapers as the depth into the gate stack increases. The inventors have devised a unique deposition scheme that compensates for etch performance degradation in deep trenches by a novel plasma-enhanced chemical vapor deposition (PECVD) film deposition method. The inventors have found that by grading various properties (e.g., refractive index, stress of the film, dopant concentration in the film) of the as-deposited films (e.g., silicon nitride) a more uniform etch profile can be achieved by compensating for variations in both dry and wet etch rates.

Abstract: A method for forming a memory device includes: providing a substrate including at least word line structures and active regions, and a bottom dielectric layer and bit line contact layers that are on a top surface of the substrate; part of the bit line contact layers are etched to form bit line contact layers at different heights; conducting layers are formed, top surfaces of the conducting layers being at different heights in a direction perpendicular to an extension direction of the word line structure, and the top surfaces of the conducting layers being at different heights in the extension direction of the word line structure; top dielectric layers are formed; and etching is performed to form separate bit line structures.

Abstract: Provided are an improved memory device and a method of manufacturing the same. In one embodiment, the memory device may include a vertical stack of alternating oxide layer and nitride layer, the vertical stack having a channel region formed therethrough, a plurality of nanostructures selectively formed on nitride layer of the vertical stack, and a gate oxide layer disposed on exposed surfaces of the channel region, the gate oxide layer encapsulating the plurality of nanostructures formed on the nitride layer. The nanostructures may be a group IV semiconductor compound such as silicon germanium (SiGe).

Abstract: Methods and apparatus for depositing a cobalt layer in a feature, such as, a word line formed in a substrate, are provided herein. In some embodiments, method of processing a substrate includes: exposing a substrate at a first temperature to a cobalt containing precursor to deposit a cobalt layer within a word line feature formed in the substrate, wherein the word line feature is part of a 3D NAND device; and annealing the substrate to remove contaminants from the cobalt layer and to reflow the cobalt layer into the word line feature, wherein the substrate is at a second temperature greater than the first temperature during the annealing.

Abstract: Methods and systems relating to processes for treating a tungsten film on a workpiece including supporting the workpiece in a chamber, introducing hydrogen gas into the chamber and establishing a pressure of at least 5 atmospheres, and exposing the tungsten film on the workpiece to the hydrogen gas while the pressure in the chamber is at least 5 atmospheres.