Patents by Inventor Thomas Joseph Richardson

Thomas Joseph Richardson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10164738
    Abstract: Encoders, decoders and methods of encoding and decoding data can comprise receiving source symbols in a first sequence, storing the source symbols to a first memory in a second sequence, wherein the first sequence is a first interlacing relative to the second sequence, determining if the memory contains all source symbols of a codeword, wherein the source symbols of a codeword are the symbols used to generate repair symbols for that codeword, generating repair symbols for the codeword, storing the repair symbols to a second memory in a third sequence, interlacing the repair symbols and the source symbols into an output stream as a stream of encoded symbols, wherein the repair symbols appear in the output stream in a fourth sequence, wherein the fourth sequence is a second interlacing relative to the third sequence, and outputting the stream of encoded symbols.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: December 25, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Thomas Joseph Richardson, Vincent Abayomi Loncke
  • Publication number: 20180234114
    Abstract: Aspects of the present disclosure relate to low density parity check (LDPC) coding utilizing a configurable circular buffer for rate matched transmissions. The circular buffer may be configured based on a selected mother code rate and a fixed circular buffer length. For example, the respective sizes of the systematic and parity bit sections of the circular buffer may be variable based on the selected mother code rate.
    Type: Application
    Filed: February 12, 2018
    Publication date: August 16, 2018
    Inventors: Joseph Binamira Soriaga, Shrinivas Kudekar, Thomas Joseph Richardson, Jing Jiang, Renqiu Wang
  • Patent number: 10044371
    Abstract: Systems and methods which implement repair bandwidth control techniques, such as may provide a feedback control structure for regulating repair bandwidth in the storage system. Embodiments control a source object repair rate in a storage system by analyzing source objects represented in a repair queue to determine repair rate metrics for the source objects and determining a repair rate based on the repair rate metrics to provide a determined level of recovery of source data stored as by the source objects and to provide a determined level of repair efficiency in the storage system. For example, embodiments may determine a per storage object repair rate (e.g., a repair rate preference for each of a plurality of source objects) and select a particular repair rate (e.g., a maximum repair rate) for use by a repair policy. Thereafter, the repair policy of embodiments may implement repair of one or more source objects in accordance with the repair rate.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: August 7, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Thomas Joseph Richardson, Michael George Luby
  • Publication number: 20180205497
    Abstract: Certain aspects of the present disclosure relate to methods and apparatus for optimizing delivery of a transport block (TB) using code rate dependent segmentation.
    Type: Application
    Filed: January 17, 2018
    Publication date: July 19, 2018
    Inventors: Renqiu WANG, Jing JIANG, Joseph Binamira SORIAGA, Thomas Joseph RICHARDSON, Vincent LONCKE
  • Patent number: 10007587
    Abstract: Systems and methods utilizing available storage space within a storage system (e.g., as “supplemental” storage) and/or implement less physical storage space in the storage system (e.g., reduced storage overhead) through operation of fragment pre-storage techniques are disclosed. Such fragment pre-storage utilization of the aforementioned available storage space may provide operation emulating larger storage overhead than is actually provided in the storage system, facilitate improved repair rates, and/or facilitate reduced repair bandwidth in the storage system according to embodiments. A fragment pre-storage repair policy may implement source object repair whereby additional fragments for the source object are pre-generated and pre-stored in the storage system as transient fragments, whereby the transient fragments are moved to corresponding storage nodes when those storage nodes become physically present in the storage system.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: June 26, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Thomas Joseph Richardson, Michael George Luby
  • Patent number: 10001944
    Abstract: Systems and methods which implement one or more data organization techniques that facilitate efficient access to source data stored by a storage system are disclosed. Data organization techniques implemented according to embodiments are adapted to optimize (e.g., maximize) input/output efficiency and/or (e.g., minimize) storage overhead, while maintaining mean time to data loss, repair efficiency, and/or traffic efficiency. Data organization techniques as may be implemented by embodiments include blob based organization techniques, grouped symbols organization techniques, data ordering organization techniques, and combinations thereof.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: June 19, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Michael George Luby, Thomas Joseph Richardson
  • Patent number: 10003357
    Abstract: Systems and methods which implement forward checking of data integrity are disclosed. A storage system of embodiments may, for example, comprise data integrity forward checking logic which is operable to perform forward checking of data integrity in real-time or near real-time to check that a number of node failures can be tolerated without loss of data. Embodiments may be utilized to provide assurance that a number of fragments needed for source data recovery will be available for the source objects most susceptible to failure when a certain number of additional fragments are lost, such as due to storage node failures.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: June 19, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Thomas Joseph Richardson, Michael George Luby, Mahdi Cheraghchi Bashi Astaneh, Lorenz Christoph Minder
  • Patent number: 9979475
    Abstract: A method, an apparatus, and a computer program product for communication are provided. The apparatus obtains a message for communication using visible light communication (VLC) through a light emitting diode (LED) luminary device and formats the message using a synchronization signal followed by one or more data signals. The synchronization signal and/or the one or more data signals are modulated using a Frequency Shift Keying (FSK) modulation scheme. The apparatus further receives a dimming level value associated with a brightness of light to be emitted from the LED luminary device, generates a waveform with frequencies based on the formatted message and a duty cycle for the LED luminary device based on the dimming level value, and sends the generated waveform to the LED luminary device for communication using VLC.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: May 22, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Aleksandar Jovicic, Thomas Joseph Richardson, Junyi Li
  • Publication number: 20180131391
    Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low density parity check (LDPC) codes, and more particularly to an efficient list decoder for list decoding low density parity check (LDPC) codes.
    Type: Application
    Filed: November 2, 2017
    Publication date: May 10, 2018
    Inventors: Shrinivas KUDEKAR, Thomas Joseph RICHARDSON, Gabi SARKIS, Vincent LONCKE
  • Publication number: 20180123734
    Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low density parity check (LDPC) codes, and more particularly to a deeply-pipelined layered LDPC decoder architecture for high decoding throughputs.
    Type: Application
    Filed: September 22, 2017
    Publication date: May 3, 2018
    Inventors: Vincent LONCKE, Girish VARATKAR, Thomas Joseph RICHARDSON, Yi CAO
  • Publication number: 20180123615
    Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low density parity check (LDPC) codes, and more particularly to non-linear log-likelihood ratio quantization techniques for low-density parity-check (LDPC) decoder architecture.
    Type: Application
    Filed: June 9, 2017
    Publication date: May 3, 2018
    Inventors: Girish VARATKAR, Vincent LONCKE, Thomas Joseph RICHARDSON, Yi CAO
  • Publication number: 20180109269
    Abstract: Certain aspects of the present disclosure generally relate to techniques for efficient, high-performance decoding of low-density parity check (LDPC) codes, for example, by using an adjusted minimum-sum (AdjMS) algorithm, which involves approximating an update function and determining magnitudes of outgoing log likelihood ratios (LLRs). Similar techniques may also be used for decoding turbo codes. Other aspects, embodiments, and features (such as encoding technique) are also claimed and described.
    Type: Application
    Filed: October 12, 2017
    Publication date: April 19, 2018
    Inventors: Thomas Joseph RICHARDSON, Shrinivas KUDEKAR, Vincent LONCKE
  • Patent number: 9939521
    Abstract: Provided are apparatus and methods for ranging between a plurality of wireless devices. An exemplary method includes, at a first wireless device, transmitting a primary portion symbol comprising a first packet and transmitting a secondary portion symbol. The secondary portion symbol is transmitted simultaneously at a lower transmit power than the primary portion symbol, and the secondary portion symbol comprises a second packet identical to the first packet. The primary portion symbol can be transmitted in a first channel having a substantially 20 MHZ bandwidth and the secondary portion can be transmitted in a second channel having a substantially 20 MHZ bandwidth. The first and second channels are substantially adjacent in frequency. After transmitting the primary portion symbol, for example, a high-throughput long-training-field symbol or a very-high-throughput long-training-field symbol can be repetitively transmitted.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: April 10, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Jubin Jose, Xinzhou Wu, Thomas Joseph Richardson
  • Patent number: 9933973
    Abstract: Systems and methods which implement one or more data organization techniques that facilitate efficient access to source data stored by a storage system are disclosed. Data organization techniques implemented according to embodiments are adapted to optimize (e.g., maximize) input/output efficiency and/or (e.g., minimize) storage overhead, while maintaining mean time to data loss, repair efficiency, and/or traffic efficiency. Data organization techniques as may be implemented by embodiments include blob based organization techniques, grouped symbols organization techniques, data ordering organization techniques, and combinations thereof.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: April 3, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Michael George Luby, Thomas Joseph Richardson
  • Patent number: 9917675
    Abstract: Certain aspects of the present disclosure relate to techniques and apparatus for improving decoding latency and performance of Polar codes. An exemplary method generally includes generating a codeword by encoding information bits, using a multi-dimensional interpretation of a polar code of length N, determining, based on one or more criteria, a plurality of locations within the codeword to insert error correction codes generating the error correction codes based on corresponding portions of the information bits, inserting the error correction codes at the determined plurality of locations, and transmitting the codeword. Other aspects, embodiments, and features are also claimed and described.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: March 13, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Shrinivas Kudekar, Thomas Joseph Richardson
  • Patent number: 9867153
    Abstract: This application relates to wireless communication systems, and more particularly to distributed synchronization of “internet of everything” (IoE) devices to a common timing through opportunistic synchronization with user equipment (UE). Multiple IoE devices within proximity to each other establish device to device (D2D) links. When an IoE device receives an updated timing synchronization signal from a UE, the IoE device can broadcast the updated timing synchronization signal to other IoE devices directly or via a multi-hop forwarding scheme via the D2D links. Multiple groups of IoE devices can be synchronized to the same timing synchronization signal such that if and when IoE devices from the different groups come into proximity, the IoE devices will find each other and can merge into a larger group of synchronized IoE devices with minimal searching overhead and, therefore, minimal power consumption.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: January 9, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Junyi Li, Jay Rodney Walton, Thomas Joseph Richardson
  • Publication number: 20170359148
    Abstract: Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low-density parity-check (LDPC) codes. Certain aspects of the present disclosure generally relate to methods and apparatus for a high-performance, flexible, and compact LDPC code. Certain aspects can enable LDPC code designs to support large ranges of rates, blocklengths, and granularity, while being capable of fine incremental redundancy hybrid automatic repeat request (IR-HARQ) extension while maintaining good floor performance, a high-level of parallelism to deliver high throughout performance, and a low description complexity.
    Type: Application
    Filed: June 13, 2017
    Publication date: December 14, 2017
    Inventors: Thomas Joseph RICHARDSON, Shrinivas KUDEKAR
  • Publication number: 20170359086
    Abstract: Certain aspects of the present disclosure generally relate to techniques for compactly describing lifted low-density parity-check (LDPC) codes. A method for wireless communications by a transmitting device is provided.
    Type: Application
    Filed: June 13, 2017
    Publication date: December 14, 2017
    Inventors: Shrinivas KUDEKAR, Thomas Joseph RICHARDSON
  • Publication number: 20170353271
    Abstract: Certain aspects of the present disclosure relate to techniques and apparatus for improving decoding latency and performance of Polar codes. An exemplary method generally includes generating a codeword by encoding information bits, using a multi-dimensional interpretation of a polar code of length N, determining, based on one or more criteria, a plurality of locations within the codeword to insert error correction codes generating the error correction codes based on corresponding portions of the information bits, inserting the error correction codes at the determined plurality of locations, and transmitting the codeword. Other aspects, embodiments, and features are also claimed and described.
    Type: Application
    Filed: December 30, 2016
    Publication date: December 7, 2017
    Inventors: Shrinivas KUDEKAR, Thomas Joseph RICHARDSON
  • Publication number: 20170353267
    Abstract: Certain aspects of the present disclosure relate to techniques and apparatus for improving decoding latency and performance of Polar codes. An exemplary method generally includes generating a codeword by encoding information bits using a first code of length K to obtain bits for transmission via K channels, wherein the first code comprises a polar code, further encoding the bits in each of the K channels using a second code of length M, and transmitting the codeword.
    Type: Application
    Filed: December 30, 2016
    Publication date: December 7, 2017
    Inventors: Shrinivas KUDEKAR, Thomas Joseph RICHARDSON