Patents by Inventor Thomas Kaempfe
Thomas Kaempfe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11637111Abstract: The present invention relates to an integrated electronic circuit and method of making comprising a first transistor (1) and a ferroelectric capacitor (2). The ferroelectric capacitor (2) comprises a first electrode layer composed of a non-ferroelectric material, a ferroelectric interlayer having a thickness that is less than the thickness of the first electrode layer, and a second electrode layer composed of a non-ferroelectric material, wherein the ferroelectric interlayer is arranged between the first electrode layer and the second electrode layer, and the first electrode layer is electrically conductively connected to a gate terminal of the first transistor (1).Type: GrantFiled: May 12, 2021Date of Patent: April 25, 2023Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FORDERUNG ANGEWANDTEN FORSCHUNG E.V.Inventors: Konrad Seidel, Thomas Kaempfe, Patrick Polakowski
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Publication number: 20230108879Abstract: A resistor network and an integrated circuit at least part of the resistor network may have at least two memory cells for storing in each case one resistance characteristic value. Each memory cell may have a first contact pair configured to provide an electrical resistance corresponding to the stored resistance characteristic value in at least one operating mode. First contacts of the respective first contact pair of the two memory cells are directly connected to one another and second contacts of the respective first contact pair of the two memory cells are electrically independent of one another. The memory cells may each have a second contact pair which is electrically independent of the first contact pair and which is arranged in such a way that the stored electrical resistance characteristic value of the respective memory cell can be reversibly changed by suitable electrical signals via this second contact pair.Type: ApplicationFiled: March 8, 2021Publication date: April 6, 2023Inventors: Maximilian LEDERER, Thomas KÄMPFE
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Publication number: 20230019457Abstract: A piezoelectric element and a method of manufacturing the piezoelectric element are provided. The piezoelectric element is provided with a substrate having an intermediate layer disposed between a first substrate layer and a second substrate layer, a first electrode layer of an electrically conductive non-ferroelectric material disposed on the second substrate layer, a ferroelectric, piezoelectric and/or flexoelectric layer disposed on the first electrode layer, and a second electrode layer of an electrically conductive non-ferroelectric material disposed on the ferroelectric, piezoelectric and/or flexoelectric layer. The intermediate layer and/or the first substrate layer is removed below a layer stack formed by the first electrode layer, the ferroelectric, piezoelectric and/or flexoelectric layer, and the second electrode layer so that the layer stack can be moved in a translatory manner along its normal directed along the layer sequence.Type: ApplicationFiled: December 18, 2020Publication date: January 19, 2023Inventor: Thomas KÄMPFE
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Publication number: 20230013976Abstract: A movable piezo element and to a method for producing the element are provided. The movable piezo element may have a structured substrate, in which an intermediate layer is arranged between a first substrate layer and a second substrate layer. The element may also have a first electrode layer. The element may also have a second electrode layer arranged on the ferroelectric, piezoelectric, or flexoelectric layer. The second substrate layer may be structured such that at least one bar of the second substrate layer is formed. The bar may be clamped on one side and may be physically spaced from the first substrate layer. A surface of the bar facing away from the first substrate layer, and/or a lateral surface of the bar, may be at least partly covered by another layer.Type: ApplicationFiled: December 18, 2020Publication date: January 19, 2023Inventors: Thomas KÄMPFE, Patrick POLAKOWSKI, Konrad SEIDEL
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Publication number: 20220373718Abstract: The present invention relates to an optical device (1) suitable for transmitting/reflecting electromagnetic radiation in a wavelength range of the electromagnetic spectrum, said device (1) comprising at least: a first coating layer (10) made of a first material, a substrate (50) made of a material that is different from the first material, and surface texturing (60) forming cavities (61) in the device (1); wherein a lower layer (50) disposed directly below the first coating layer (10) is either a second coating layer (20) made of a material that is different from the first material, or the substrate (50); wherein the lower layer (50) has a determined thickness (E50); characterised in that the cavities (61) extend through the coating layer (20) and are sunk into the lower layer (50) through at least part of the thickness (E50).Type: ApplicationFiled: October 26, 2020Publication date: November 24, 2022Applicants: Hydromecanique et Frottement, Manutech-USD, Université Jean Monnet Saint-Etienne, Centre National de la Recherche ScientifiqueInventors: Thomas KÄMPFE, Laurent DUBOST, Xxx SEDAO
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Publication number: 20220365249Abstract: The present invention relates to an optical device (1), suitable for transmitting/reflecting electromagnetic radiation in a wavelength range of the electromagnetic spectrum, said device (1) comprising at least: a substrate (10) made of a first material, a coating layer (20) made of a second material that is different from the first material, and surface texturing (30) forming cavities (31) in the device (1), characterized in that the cavities (31) extend through the coating layer (20) and are partially sunk into the substrate (10).Type: ApplicationFiled: October 26, 2020Publication date: November 17, 2022Applicants: Hydromecanique et Frottement, Manutech-USD, Université Jean Monnet Saint-Etienne, Centre National de la Recherche ScientifiqueInventors: Thomas KÄMPFE, Laurent DUBOST, Xxx SEDAO
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Patent number: 11121266Abstract: The present invention relates to a voltage-controllable capacitor comprising a first electrode layer (4) composed of a non-ferroelectric material, said first electrode layer being applied on a substrate (6), a ferroelectric interlayer (3) having a thickness that is less than the thickness of the first electrode layer (4), and a second electrode layer (2) composed of a non-ferroelectric material. The ferroelectric interlayer (3) is arranged between the first electrode layer (4) and the second electrode layer (2).Type: GrantFiled: August 2, 2019Date of Patent: September 14, 2021Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.Inventors: Thomas Kaempfe, Patrick Polakowski, Konrad Seidel
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Publication number: 20210265367Abstract: The present invention relates to an integrated electronic circuit and method of making comprising a first transistor (1) and a ferroelectric capacitor (2). The ferroelectric capacitor (2) comprises a first electrode layer composed of a non-ferroelectric material, a ferroelectric interlayer having a thickness that is less than the thickness of the first electrode layer, and a second electrode layer composed of a non-ferroelectric material, wherein the ferroelectric interlayer is arranged between the first electrode layer and the second electrode layer, and the first electrode layer is electrically conductively connected to a gate terminal of the first transistor (1).Type: ApplicationFiled: May 12, 2021Publication date: August 26, 2021Applicant: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.Inventors: Konrad SEIDEL, Thomas Kaempfe, Patrick Polakowski
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Patent number: 11018146Abstract: The present invention relates to an integrated electronic circuit comprising a first transistor (1) and a ferroelectric capacitor (2). The ferroelectric capacitor (2) comprises a first electrode layer composed of a non-ferroelectric material, a ferroelectric interlayer having a thickness that is less than the thickness of the first electrode layer, and a second electrode layer composed of a non-ferroelectric material, wherein the ferroelectric interlayer is arranged between the first electrode layer and the second electrode layer, and the first electrode layer is electrically conductively connected to a gate terminal of the first transistor (1).Type: GrantFiled: August 2, 2019Date of Patent: May 25, 2021Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERTJNG DER ANGEWANDTEN FORSCHUNG E.V.Inventors: Konrad Seidel, Thomas Kaempfe, Patrick Polakowski
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Publication number: 20200044097Abstract: The present invention relates to a voltage-controllable capacitor comprising a first electrode layer (4) composed of a non-ferroelectric material, said first electrode layer being applied on a substrate (6), a ferroelectric interlayer (3) having a thickness that is less than the thickness of the first electrode layer (4), and a second electrode layer (2) composed of a non-ferroelectric material. The ferroelectric interlayer (3) is arranged between the first electrode layer (4) and the second electrode layer (2).Type: ApplicationFiled: August 2, 2019Publication date: February 6, 2020Applicant: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.Inventors: Thomas KAEMPFE, Patrick POLAKOWSKI, Konrad SEIDEL
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Publication number: 20200043938Abstract: The present invention relates to an integrated electronic circuit comprising a first transistor (1) and a ferroelectric capacitor (2). The ferroelectric capacitor (2) comprises a first electrode layer composed of a non-ferroelectric material, a ferroelectric interlayer having a thickness that is less than the thickness of the first electrode layer, and a second electrode layer composed of a non-ferroelectric material, wherein the ferroelectric interlayer is arranged between the first electrode layer and the second electrode layer, and the first electrode layer is electrically conductively connected to a gate terminal of the first transistor (1).Type: ApplicationFiled: August 2, 2019Publication date: February 6, 2020Applicant: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.Inventors: Konrad SEIDEL, Thomas KAEMPFE, Patrick POLAKOWSKI
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Patent number: 9389351Abstract: The planar polarization transformer for a normally incident optical wave or beam having a given vacuum wavelength ? comprises an optical planar grating between a cover medium of refractive index nc and an optical substrate of refractive index ns, this planar grating defining a binary index modulation or corrugation of substantially rectangular profile with periodic ridges. This polarization transformer is characterized in that the ridge refractive index nr is larger than the substrate refractive index ns, the grating period ? is larger than 0.4·?/nc, the substrate refractive index ns is smaller than 2.7·nc, and the index modulation or corrugation is designed such that, according to the grating mode dispersion equation, the effective index of the mode TE0 is larger than the substrate index ns and the effective index of the mode TM0 is larger than the cover refractive index and smaller than the substrate index.Type: GrantFiled: May 31, 2012Date of Patent: July 12, 2016Assignee: Université Jean-MonnetInventors: Thomas Kaempfe, Olivier Parriaux
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Publication number: 20140146390Abstract: The planar polarization transformer for a normally incident optical wave or beam having a given vacuum wavelength ? comprises an optical planar grating between a cover medium of refractive index nc and an optical substrate of refractive index ns, this planar grating defining a binary index modulation or corrugation of substantially rectangular profile with periodic ridges. This polarization transformer is characterized in that the ridge refractive index nr is larger than the substrate refractive index ns, the grating period ? is larger than 0.4·?/nc, the substrate refractive index ns is smaller than 2.7·nc, and the index modulation or corrugation is designed such that, according to the grating mode dispersion equation, the effective index of the mode TE0 is larger than the substrate index ns and the effective index of the mode TM0 is larger than the cover refractive index and smaller than the substrate index.Type: ApplicationFiled: May 31, 2012Publication date: May 29, 2014Applicant: UNIVERSITÉ JEAN-MONNETInventors: Thomas Kaempfe, Olivier Parriaux
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Publication number: 20120262787Abstract: A diffractive optical element generates a phase distribution with an arbitrary quasi-continuous phase deviation. The diffractive optical element includes a plurality of pixels configured to generate an adjustable phase deviation. Each pixel has a base face, and the plurality of pixels being disposed adjacent each other with their base faces in an element plane of the diffractive optical element. One or more pixels of the plurality of pixels includes a height profile formed by a first face and a second face of the one or more pixels. A distance between the first face and second face defining a height step that is tuned to an adjustable maximum phase deviation of the diffractive optical element.Type: ApplicationFiled: August 13, 2010Publication date: October 18, 2012Applicant: FRIEDRICH-SCHILLER-UNIVERSITÄTInventors: Uwe Detlef Zeitner, Dirk Michaelis, Ernst-Bernhard Kley, Thomas Kämpfe, Wiebke Freese