Abstract: The disclosure relates to a method for mapping an input vector to an output vector by means of a matrix circuit which has memory cells arranged in a matrix in a plurality of rows and a plurality of columns and first, second and third lines, each memory cell having an adjustable memory state, is connected to the first line (22) of the corresponding row, is connected to the second and third lines of the corresponding column and is set up to generate an electrical current (I1, I2, I3) depending on the memory state and voltages applied to the first, second and third lines, is connected to the second and third lines of the corresponding column and is arranged to conduct an electric current (I1, I2, I3) into the third line (26) as a function of the memory state and voltages applied to the first, second and third lines, each memory cell having a semiconductor switching element (28) with a control terminal which is connected to the second line (24) of the corresponding column; wherein input voltages (U1, U2, U3) corr

Abstract: The present invention relates to an integrated electronic circuit and method of making comprising a first transistor (1) and a ferroelectric capacitor (2). The ferroelectric capacitor (2) comprises a first electrode layer composed of a non-ferroelectric material, a ferroelectric interlayer having a thickness that is less than the thickness of the first electrode layer, and a second electrode layer composed of a non-ferroelectric material, wherein the ferroelectric interlayer is arranged between the first electrode layer and the second electrode layer, and the first electrode layer is electrically conductively connected to a gate terminal of the first transistor (1).

Abstract: The present invention relates to a voltage-controllable capacitor comprising a first electrode layer (4) composed of a non-ferroelectric material, said first electrode layer being applied on a substrate (6), a ferroelectric interlayer (3) having a thickness that is less than the thickness of the first electrode layer (4), and a second electrode layer (2) composed of a non-ferroelectric material. The ferroelectric interlayer (3) is arranged between the first electrode layer (4) and the second electrode layer (2).

Abstract: The present invention relates to an integrated electronic circuit and method of making comprising a first transistor (1) and a ferroelectric capacitor (2). The ferroelectric capacitor (2) comprises a first electrode layer composed of a non-ferroelectric material, a ferroelectric interlayer having a thickness that is less than the thickness of the first electrode layer, and a second electrode layer composed of a non-ferroelectric material, wherein the ferroelectric interlayer is arranged between the first electrode layer and the second electrode layer, and the first electrode layer is electrically conductively connected to a gate terminal of the first transistor (1).

Abstract: The present invention relates to an integrated electronic circuit comprising a first transistor (1) and a ferroelectric capacitor (2). The ferroelectric capacitor (2) comprises a first electrode layer composed of a non-ferroelectric material, a ferroelectric interlayer having a thickness that is less than the thickness of the first electrode layer, and a second electrode layer composed of a non-ferroelectric material, wherein the ferroelectric interlayer is arranged between the first electrode layer and the second electrode layer, and the first electrode layer is electrically conductively connected to a gate terminal of the first transistor (1).

Abstract: The planar polarization transformer for a normally incident optical wave or beam having a given vacuum wavelength ? comprises an optical planar grating between a cover medium of refractive index nc and an optical substrate of refractive index ns, this planar grating defining a binary index modulation or corrugation of substantially rectangular profile with periodic ridges. This polarization transformer is characterized in that the ridge refractive index nr is larger than the substrate refractive index ns, the grating period ? is larger than 0.4·?/nc, the substrate refractive index ns is smaller than 2.7·nc, and the index modulation or corrugation is designed such that, according to the grating mode dispersion equation, the effective index of the mode TE0 is larger than the substrate index ns and the effective index of the mode TM0 is larger than the cover refractive index and smaller than the substrate index.

Abstract: The planar polarization transformer for a normally incident optical wave or beam having a given vacuum wavelength ? comprises an optical planar grating between a cover medium of refractive index nc and an optical substrate of refractive index ns, this planar grating defining a binary index modulation or corrugation of substantially rectangular profile with periodic ridges. This polarization transformer is characterized in that the ridge refractive index nr is larger than the substrate refractive index ns, the grating period ? is larger than 0.4·?/nc, the substrate refractive index ns is smaller than 2.7·nc, and the index modulation or corrugation is designed such that, according to the grating mode dispersion equation, the effective index of the mode TE0 is larger than the substrate index ns and the effective index of the mode TM0 is larger than the cover refractive index and smaller than the substrate index.