Patents by Inventor Thomas Kalla
Thomas Kalla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240111933Abstract: A computer implemented method for automated generation and verification of a technology specific logic model and a technology independent logic model of a memory array, the method at least comprising: having a first set of parameters; having a set of constraints, creating a second set of parameters; generating the technology independent model of the memory array wherein the second set of parameters and the set of constraints are used; generating the technology specific model of the memory array wherein the first set of parameters and the set of constraints are used; verifying the technology independent model and the technology specific model for equivalence on a sequential logic basis.Type: ApplicationFiled: September 29, 2022Publication date: April 4, 2024Inventors: Thomas Kalla, Jentje Leenstra, Richard Louis Henry Carbone, Philipp Salz
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Patent number: 10586006Abstract: Generating design data for manufacturing a logic array of a semiconductor circuit from specification data describing the logic array. The specification is transformed into structured specification data including objects corresponding to circuit cells of a first type and logic specification data specifying the logic circuitry to be included in the logic array, and into structure data including placing and routing information concerning the circuit cells of the first type. A determination is made of circuit cells of a second type from the logic specification data. The circuit cells of the first type are pre-placed and routed based on the structure data. The circuit cells of second type are automatically placed and routed.Type: GrantFiled: April 24, 2019Date of Patent: March 10, 2020Assignee: International Business Machines CorporationInventors: Albert Frisch, Thomas Kalla, Juergen Pille, Philipp Salz
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Patent number: 10388357Abstract: In an approach to activating at least one memory core circuit of a plurality of memory core circuits in an integrated circuit, one or more computer processors activate a clock signal of a currently selected memory core circuit. The one or more computer processors activate the clock signal of a previously selected memory core circuit to allow the previously selected memory core circuit to be set to a deselected operating mode. The one or more computer processors forward an output bit generated by a memory core circuit selected from a plurality of memory core circuits to a multiplexed bit line.Type: GrantFiled: December 5, 2017Date of Patent: August 20, 2019Assignee: International Business Machines CorporationInventors: Thomas Kalla, Jens Noack, Juergen Pille, Philipp Salz
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Publication number: 20190251221Abstract: Generating design data for manufacturing a logic array of a semiconductor circuit from specification data describing the logic array. The specification is transformed into structured specification data including objects corresponding to circuit cells of a first type and logic specification data specifying the logic circuitry to be included in the logic array, and into structure data including placing and routing information concerning the circuit cells of the first type. A determination is made of circuit cells of a second type from the logic specification data. The circuit cells of the first type are pre-placed and routed based on the structure data. The circuit cells of second type are automatically placed and routed.Type: ApplicationFiled: April 24, 2019Publication date: August 15, 2019Inventors: Albert Frisch, Thomas Kalla, Juergen Pille, Philipp Salz
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Publication number: 20190228811Abstract: In an approach to activating at least one memory core circuit of a plurality of memory core circuits in an integrated circuit, one or more computer processors activate a clock signal of a currently selected memory core circuit. The one or more computer processors activate the clock signal of a previously selected memory core circuit to allow the previously selected memory core circuit to be set to a deselected operating mode. The one or more computer processors forward an output bit generated by a memory core circuit selected from a plurality of memory core circuits to a multiplexed bit line.Type: ApplicationFiled: April 1, 2019Publication date: July 25, 2019Inventors: Thomas Kalla, Jens Noack, Juergen Pille, Philipp Salz
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Patent number: 10318688Abstract: Generating design data for manufacturing a logic array of a semiconductor circuit from specification data describing the logic array. The specification is transformed into structured specification data including objects corresponding to circuit cells of a first type and logic specification data specifying the logic circuitry to be included in the logic array, and into structure data including placing and routing information concerning the circuit cells of the first type. A determination is made of circuit cells of a second type from the logic specification data. The circuit cells of the first type are pre-placed and routed based on the structure data. The circuit cells of second type are automatically placed and routed.Type: GrantFiled: March 27, 2017Date of Patent: June 11, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Albert Frisch, Thomas Kalla, Juergen Pille, Philipp Salz
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Patent number: 10210923Abstract: In an approach to activating at least one memory core circuit of a plurality of memory core circuits in an integrated circuit, one or more computer processors activate a clock signal of a currently selected memory core circuit. The one or more computer processors activate the clock signal of a previously selected memory core circuit to allow the previously selected memory core circuit to be set to a deselected operating mode. The one or more computer processors forward an output bit generated by a memory core circuit selected from a plurality of memory core circuits to a multiplexed bit line.Type: GrantFiled: July 12, 2017Date of Patent: February 19, 2019Assignee: International Business Machines CorporationInventors: Thomas Kalla, Jens Noack, Juergen Pille, Philipp Salz
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Patent number: 10204674Abstract: In an approach to activating at least one memory core circuit of a plurality of memory core circuits in an integrated circuit, one or more computer processors activate a clock signal of a currently selected memory core circuit. The one or more computer processors activate the clock signal of a previously selected memory core circuit to allow the previously selected memory core circuit to be set to a deselected operating mode. The one or more computer processors forward an output bit generated by a memory core circuit selected from a plurality of memory core circuits to a multiplexed bit line.Type: GrantFiled: December 22, 2017Date of Patent: February 12, 2019Assignee: International Business Machines CorporationInventors: Thomas Kalla, Jens Noack, Juergen Pille, Philipp Salz
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Publication number: 20190019548Abstract: In an approach to activating at least one memory core circuit of a plurality of memory core circuits in an integrated circuit, one or more computer processors activate a clock signal of a currently selected memory core circuit. The one or more computer processors activate the clock signal of a previously selected memory core circuit to allow the previously selected memory core circuit to be set to a deselected operating mode. The one or more computer processors forward an output bit generated by a memory core circuit selected from a plurality of memory core circuits to a multiplexed bit line.Type: ApplicationFiled: December 5, 2017Publication date: January 17, 2019Inventors: Thomas Kalla, Jens Noack, Juergen Pille, Philipp Salz
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Publication number: 20190019547Abstract: In an approach to activating at least one memory core circuit of a plurality of memory core circuits in an integrated circuit, one or more computer processors activate a clock signal of a currently selected memory core circuit. The one or more computer processors activate the clock signal of a previously selected memory core circuit to allow the previously selected memory core circuit to be set to a deselected operating mode. The one or more computer processors forward an output bit generated by a memory core circuit selected from a plurality of memory core circuits to a multiplexed bit line.Type: ApplicationFiled: July 12, 2017Publication date: January 17, 2019Inventors: Thomas Kalla, Jens Noack, Juergen Pille, Philipp Salz
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Publication number: 20190019549Abstract: In an approach to activating at least one memory core circuit of a plurality of memory core circuits in an integrated circuit, one or more computer processors activate a clock signal of a currently selected memory core circuit. The one or more computer processors activate the clock signal of a previously selected memory core circuit to allow the previously selected memory core circuit to be set to a deselected operating mode. The one or more computer processors forward an output bit generated by a memory core circuit selected from a plurality of memory core circuits to a multiplexed bit line.Type: ApplicationFiled: December 22, 2017Publication date: January 17, 2019Inventors: Thomas Kalla, Jens Noack, Juergen Pille, Philipp Salz
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Publication number: 20180068043Abstract: Generating design data for manufacturing a logic array of a semiconductor circuit from specification data describing the logic array. The specification is transformed into structured specification data including objects corresponding to circuit cells of a first type and logic specification data specifying the logic circuitry to be included in the logic array, and into structure data including placing and routing information concerning the circuit cells of the first type. A determination is made of circuit cells of a second type from the logic specification data. The circuit cells of the first type are pre-placed and routed based on the structure data. The circuit cells of second type are automatically placed and routed.Type: ApplicationFiled: March 27, 2017Publication date: March 8, 2018Inventors: Albert Frisch, Thomas Kalla, Juergen Pille, Philipp Salz
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Patent number: 9837143Abstract: Embodiments of the present invention provide systems and methods for reducing power consumption during the operation of a SRAM cell. Embodiments of the present invention reduce power consumption by determining switching activity, and based off a determination of low switching activity, gates off a core which is not written; and limits switching activity on the unaddressed core by applying the highest order bit.Type: GrantFiled: October 12, 2016Date of Patent: December 5, 2017Assignee: International Business Machines CorporationInventors: Hans-Werner Anderson, Thomas Kalla, Jens Noack, Holger Wetter
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Patent number: 8756538Abstract: A method for implementing a hardware design that includes using a computer for receiving structured data that includes a representation of a basic hardware structure and a complex hardware structure that includes the basic hardware structure, parsing the structured data and generating, based on a result of the parsing, commands of a hardware design environment.Type: GrantFiled: February 19, 2013Date of Patent: June 17, 2014Assignee: International Business Machines CorporationInventors: Hans-Werner Anderson, Uwe Brandt, Markus Buehler, Katherine Eve, Thomas Kalla, Jens Noack, Monika Strohmer