Abstract: Systems and methods disclosed herein include a device with a bulk acoustic wave resonator and one or more trenches that are configured to impede the flow of acoustic energy to the bulk acoustic wave resonator.

Abstract: A sensing device includes an anchor having a central axis that defines a first radial direction and a second radial direction, and a resonant member flexibly supported by the anchor that includes a main body made of a single-crystal solid. The main body has a first material stiffness in the first radial direction and a second material stiffness in the second radial direction that is less than the first material stiffness. Moreover, the main body has a first component stiffness in the first radial direction and a second component stiffness in the second radial direction that is substantially similar to the first component stiffness. Another sensing device includes a resonant member having a main body that defines an aperture extending through the main body, and an electrode located in the aperture such that a capacitive channel is defined between the electrode and the main body that circumscribes the electrode.

Abstract: A sensing device includes an anchor having a central axis that defines a first radial direction and a second radial direction, and a resonant member flexibly supported by the anchor that includes a main body made of a single-crystal solid. The main body has a first material stiffness in the first radial direction and a second material stiffness in the second radial direction that is less than the first material stiffness. Moreover, the main body has a first component stiffness in the first radial direction and a second component stiffness in the second radial direction that is substantially similar to the first component stiffness. Another sensing device includes a resonant member having a main body that defines an aperture extending through the main body, and an electrode located in the aperture such that a capacitive channel is defined between the electrode and the main body that circumscribes the electrode.

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor layer having a first-type region and a second-type region that are stacked and interface with each other to form a p-n junction, the first-type region defining a first side of the semiconductor layer and the second-type region defining a second side of the semiconductor layer. The method further includes providing an insulating layer on the second side of the semiconductor layer and etching the semiconductor layer from the first side of the semiconductor layer toward the second side of the semiconductor layer to form a trench. The first-type region corresponds to one of a n-type region and a p-type region, and the second-type region corresponds to the other of the n-type region and the p-type region.

Abstract: A sensing device includes an anchor having a central axis that defines a first radial direction and a second radial direction, and a resonant member flexibly supported by the anchor that includes a main body made of a single-crystal solid. The main body has a first material stiffness in the first radial direction and a second material stiffness in the second radial direction that is less than the first material stiffness. Moreover, the main body has a first component stiffness in the first radial direction and a second component stiffness in the second radial direction that is substantially similar to the first component stiffness. Another sensing device includes a resonant member having a main body that defines an aperture extending through the main body, and an electrode located in the aperture such that a capacitive channel is defined between the electrode and the main body that circumscribes the electrode.

Abstract: Integrated circuit substrates having through silicon vias (TSVs) are described. The TSVs are vias extending through the silicon substrate in which the integrated circuitry is formed. The TSVs may be formed prior to formation of the integrated circuitry on the integrated circuit substrate, allowing the use of via materials which can be fabricated at relatively small sizes. The integrated circuit substrates may be bonded with a substrate having a microelectromechanical systems (MEMS) device. In some such situations, the circuitry of the integrated circuit substrate may face away from the MEMS substrate since the TSVs may provide electrical connection from the circuitry side of the integrated circuit substrate to the MEMS device.

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor layer having a first-type region and a second-type region that are stacked and interface with each other to form a p-n junction, the first-type region defining a first side of the semiconductor layer and the second-type region defining a second side of the semiconductor layer. The method further includes providing an insulating layer on the second side of the semiconductor layer and etching the semiconductor layer from the first side of the semiconductor layer toward the second side of the semiconductor layer to form a trench. The first-type region corresponds to one of a n-type region and a p-type region, and the second-type region corresponds to the other of the n-type region and the p-type region.

Abstract: One or more conductive shielding plates are formed in a standard ASIC wafer top metal layer, e.g., for blocking cross-talk from MEMS device structure(s) on the MEMS wafer to circuitry on the ASIC wafer when the MEMS device is capped directly by the ASIC wafer in a wafer-level chip scale package. Generally speaking, a shielding plate should be at least slightly larger than the MEMS device structure it is shielding (e.g., a movable MEMS structure such as an accelerometer proof mass or a gyroscope resonator), and the shielding plate cannot be in contact with the MEMS device structure during or after wafer bonding. Thus, a recess is formed to ensure that there is sufficient cavity space away from the top surface of the MEMS device structure. The shielding plate is electrically conductive and can be biased, e.g., to the same voltage as the opposing MEMS device structure in order to maintain zero electrostatic attraction force between the MEMS device structure and the shielding plate.

Abstract: Integrated circuit substrates having through silicon vias (TSVs) are described. The TSVs are vias extending through the silicon substrate in which the integrated circuitry is formed. The TSVs may be formed prior to formation of the integrated circuitry on the integrated circuit substrate, allowing the use of via materials which can be fabricated at relatively small sizes. The integrated circuit substrates may be bonded with a substrate having a microelectromechanical systems (MEMS) device. In some such situations, the circuitry of the integrated circuit substrate may face away from the MEMS substrate since the TSVs may provide electrical connection from the circuitry side of the integrated circuit substrate to the MEMS device.

Abstract: A single photo mask can be used to define the three critical layers for the piezoelectric MEMS device, specifically the top electrode layer, the piezoelectric material layer, and the bottom electrode layer. Using a single photo mask removes the misalignment source caused by using multiple photo masks. Furthermore, in certain exemplary embodiments, all electrical interconnects use underpass interconnect. This simplifies the process for defining the device electrodes and the process sequence for achieving self-alignment between the piezoelectric element and the top and bottom electrodes. This self-alignment is achieved by using an oxide hard mask to etch the critical region of the top electrode, the piezoelectric material, and the bottom electrode with one mask and different etch chemistries depending on the layer being etched.

Abstract: A capped micromachined device has a movable micromachined structure in a first hermetic chamber and one or more interconnections in a second hermetic chamber that is hermetically isolated from the first hermetic chamber, and a barrier layer on its cap where the cap faces the first hermetic chamber, such that the first hermetic chamber is isolated from outgassing from the cap.

Abstract: One or more stopper features (e.g., bump structures) are formed in a standard ASIC wafer top passivation layer for preventing MEMS device stiction vertically in integrated devices having a MEMS device capped directly by an ASIC wafer. A TiN coating may be used on the stopper feature(s) for anti-stiction. An electrical potential may be applied to the TiN anti-stiction coating of one or more stopper features.

Abstract: A method of fabricating a MEMS device provides a device substrate, forms a plurality of trenches in/on the substrate, and forms a sacrificial material on the substrate (e.g., growing or depositing the sacrificial material) to form a plurality of etch channels. Each trench defines one etch channel, and each etch channel forms an interior configured to channel etchant. The method also bonds a handle substrate to the sacrificial material of the device substrate, and removes at least a portion of the sacrificial material.

Abstract: A method of fabricating a MEMS device provides a device substrate, forms a plurality of trenches in/on the substrate, and forms a sacrificial material on the substrate (e.g., growing or depositing the sacrificial material) to form a plurality of etch channels. Each trench defines one etch channel, and each etch channel forms an interior configured to channel etchant. The method also bonds a handle substrate to the sacrificial material of the device substrate, and removes at least a portion of the sacrificial material.

Abstract: A single photo mask can be used to define the three critical layers for the piezoelectric MEMS device, specifically the top electrode layer, the piezoelectric material layer, and the bottom electrode layer. Using a single photo mask removes the misalignment source caused by using multiple photo masks. Furthermore, in certain exemplary embodiments, all electrical interconnects use underpass interconnect. This simplifies the process for defining the device electrodes and the process sequence for achieving self-alignment between the piezoelectric element and the top and bottom electrodes. This self-alignment is achieved by using an oxide hard mask to etch the critical region of the top electrode, the piezoelectric material, and the bottom electrode with one mask and different etch chemistries depending on the layer being etched.

Abstract: A microchip has a base die with a conductive interconnect and an isolation trench around at least a portion of the conductive interconnect, and a cap die secured to the base die. A seal, formed from a metal material, is positioned between the base die and the cap die to secure them together. The microchip also has a blocking apparatus, between the isolation trench and the metal seal, that at least in part prevents the metal material from contacting the interconnect.

Abstract: A method for forming an alignment feature for back side wafer processing in a wafer fabrication process involves forming a trench into but not entirely through a wafer from a top side of the wafer; forming a contrasting material on surfaces of the trench; and grinding a bottom side of the wafer to expose the trench using the handling wafer to handle the wafer during such grinding, wherein the contrasting material lining the exposed trench provides an alignment reference for precise alignment of the wafer for back side processing the wafer.

Abstract: A capped micromachined device has a movable micromachined structure in a first hermetic chamber and one or more interconnections in a second hermetic chamber that is hermetically isolated from the first hermetic chamber, and a barrier layer on its cap where the cap faces the first hermetic chamber, such that the first hermetic chamber is isolated from outgassing from the cap.

Abstract: A method for forming an alignment feature for back side wafer processing in a wafer fabrication process involves forming a trench into but not entirely through a wafer from a top side of the wafer; forming a contrasting material on surfaces of the trench; and grinding a bottom side of the wafer to expose the trench using the handling wafer to handle the wafer during such grinding, wherein the contrasting material lining the exposed trench provides an alignment reference for precise alignment of the wafer for back side processing the wafer.

Abstract: One or more stopper features (e.g., bump structures) are formed in a standard ASIC wafer top passivation layer for preventing MEMS device stiction vertically in integrated devices having a MEMS device capped directly by an ASIC wafer. A TiN coating may be used on the stopper feature(s) for anti-stiction. An electrical potential may be applied to the TiN anti-stiction coating of one or more stopper features.