Abstract: Some embodiments of the present invention are generally directed to testing connections of a memory device to a circuit board or other device. In one embodiment, a memory device that is configured to facilitate continuity testing between the device and a printed circuit board or other device is disclosed. The memory device includes a substrate and two connection pads that are electrically coupled to one another via a test path. A system and method for testing the connections between a memory device and a circuit board or other device are also disclosed, as are additional techniques for detecting excess temperature and enabling special functionalities using multi-stage connection pads.

Abstract: Some embodiments of the present invention are generally directed to testing connections of a memory device to a circuit board or other device. In one embodiment, a memory device that is configured to facilitate continuity testing between the device and a printed circuit board or other device is disclosed. The memory device includes a substrate and two connection pads that are electrically coupled to one another via a test path. A system and method for testing the connections between a memory device and a circuit board or other device are also disclosed, as are additional techniques for detecting excess temperature and enabling special functionalities using multi-stage connection pads.

Abstract: Some embodiments of the present invention are generally directed to testing connections of a memory device to a circuit board or other device. In one embodiment, a memory device that is configured to facilitate continuity testing between the device and a printed circuit board or other device is disclosed. The memory device includes a substrate and two connection pads that are electrically coupled to one another via a test path. A system and method for testing the connections between a memory device and a circuit board or other device are also disclosed, as are additional techniques for detecting excess temperature and enabling special functionalities using multi-stage connection pads.

Abstract: Some embodiments of the present invention are generally directed to testing connections of a memory device to a circuit board or other device. In one embodiment, a memory device that is configured to facilitate continuity testing between the device and a printed circuit board or other device is disclosed. The memory device includes a substrate and two connection pads that are electrically coupled to one another via a test path. A system and method for testing the connections between a memory device and a circuit board or other device are also disclosed, as are additional techniques for detecting excess temperature and enabling special functionalities using multi-stage connection pads.

Abstract: A method comprising coupling a device to a printed circuit board, one of the device or the printed circuit board having a first connection pad and a second connection pad. The first and second connection pads are directly electrically coupled to one another, without any intervening components between the first and second connection pads, via a test path. The method further comprises performing a continuity test across the first and second connection pads and the test path and disabling the test path between the first and second connection pads.

Abstract: Disclosed is a computer-implemented method of generating a service contract for a shipping product. The method comprises: receiving information indicative of a requested shipping product; verifying an availability of the requested shipping product by means of an electronic product catalogue; receiving a tariff corresponding to the requested shipping product from a tariff system; receiving cost information about a cost of the requested shipping product from the electronic catalogue system; providing a user interface for allowing an operator to determine a price proposal based on the received tariff and the received cost information; generating a service contract based on the determined price proposal.

Abstract: Some embodiments of the present invention are generally directed to testing connections of a memory device to a circuit board or other device. In one embodiment, a memory device that is configured to facilitate continuity testing between the device and a printed circuit board or other device is disclosed. The memory device includes a substrate and two connection pads that are electrically coupled to one another via a test path. A system and method for testing the connections between a memory device and a circuit board or other device are also disclosed, as are additional techniques for detecting excess temperature and enabling special functionalities using multi-stage connection pads.

Abstract: Embodiments of the present invention are generally directed to testing connections of a memory device to a circuit board or other device. In one embodiment, a memory device that is configured to facilitate continuity testing between the device and a printed circuit board or other device is disclosed. The memory device includes a substrate and two connection pads that are electrically coupled to one another via a test path. A system and method for testing the connections between a memory device and a circuit board or other device are also disclosed.

Abstract: Semiconductor device assemblies include elements such as electronic components and substrates secured together by a fastener that includes an elongated portion extending continuously through an aperture in two or more such elements. Computer systems include such semiconductor device assemblies. Fasteners for securing together such elements include an elongated portion, a first end piece, and a second end piece. Methods of securing together a plurality of semiconductor devices include inserting an elongated portion of a fastener through an aperture in a first semiconductor device and an aperture in at least one additional semiconductor device. Circuit boards include a plurality of apertures disposed in an array corresponding to an array of apertures in a semiconductor device assembly. Each aperture is sized and configured to receive a fastener for maintaining an assembled relationship between the semiconductor device assembly and the circuit board.

Abstract: Embodiments of the present invention are generally directed to testing connections of a memory device to a circuit board or other device. In one embodiment, a memory device that is configured to facilitate continuity testing between the device and a printed circuit board or other device is disclosed. The memory device includes a substrate and two connection pads that are electrically coupled to one another via a test path. A system and method for testing the connections between a memory device and a circuit board or other device are also disclosed.

Abstract: An edge connector, system, printed circuit board and electronic module are described, which include an edge connector comprised of a substrate, including a first major exterior surface, a second major exterior surface, and a minor exterior surface. The edge connector further includes at least one of a first conductive contact affixed to the first major exterior surface and one of a second conductive contact affixed to the second major exterior surface. Additionally, the edge connector includes at least one third conductive contact conductively coupled to at least a portion of any internal conductive layer of the substrate and the third conductive contact is configured off-plane from the minor exterior surface.

Abstract: A dynamic random access memory device includes a mode register that is programmed with a delay value. In some embodiments, a offset code is also stored in the memory device. The memory device uses the delay value, which may be added to or multiplied by the offset code, to delay the initiation of a received auto-refresh or self-refresh command. A large number of dynamic random access memory devices in a system may be provided with different delay values and possibly offset codes so that the memory device do not all perform refreshes simultaneously in response to an auto-refresh or self-refresh command issued to all of the memory devices simultaneously. As a result, the peak current drawn by the memory devices resulting from the auto-refresh command or self-refresh command is maintained at a relatively low value.

Abstract: A method of forming a stacked memory module from a plurality of memory devices is provided. Each of the plurality of memory devices is modified to include a logic block for decoding a plurality of chip select signals. A first high density memory module is also provided that includes the modified memory devices and a serial presence detect device. The first high density memory module is included within an electronic system. Also, an additional method of forming a stacked memory module is provided, the method requiring modification of an address buffer to include a logic block for decoding a plurality of chip select signals. A second high density memory module is also provided that includes the modified address buffer and a serial presence detect device. The second high density memory module is included within an electronic system.

Abstract: An edge connector, system, printed circuit board and electronic module are described, which include an edge connector comprised of a substrate, including a first major exterior surface, a second major exterior surface, and a minor exterior surface. The edge connector further includes at least one of a first conductive contact affixed to the first major exterior surface and one of a second conductive contact affixed to the second major exterior surface. Additionally, the edge connector includes at least one third conductive contact conductively coupled to at least a portion of any internal conductive layer of the substrate and the third conductive contact is configured off-plane from the minor exterior surface.

Abstract: A method of forming a stacked memory module from a plurality of memory devices is provided. Each of the plurality of memory devices is modified to include a logic block for decoding a plurality of chip select signals. A first high density memory module is also provided that includes the modified memory devices and a serial presence detect device. The first high density memory module is included within an electronic system. Also, an additional method of forming a stacked memory module is provided, the method requiring modification of an address buffer to include a logic block for decoding a plurality of chip select signals. A second high density memory module is also provided that includes the modified address buffer and a serial presence detect device. The second high density memory module is included within an electronic system.

Abstract: A dynamic random access memory device includes a mode register that is programmed with a delay value. In some embodiments, a offset code is also stored in the memory device. The memory device uses the delay value, which may be added to or multiplied by the offset code, to delay the initiation of a received auto-refresh or self-refresh command. A large number of dynamic random access memory devices in a system may be provided with different delay values and possibly offset codes so that the memory device do not all perform refreshes simultaneously in response to an auto-refresh or self-refresh command issued to all of the memory devices simultaneously. As a result, the peak current drawn by the memory devices resulting from the auto-refresh command or self-refresh command is maintained at a relatively low value.