Abstract: A method and a device for operand processing in a processing unit having at least two execution units, which are able to be operated at a predefinable clock cycle. The execution units are controlled by control signals for the processing of the operands and a switch is possible between a first operating mode and a second operating mode. In the first operating mode, both execution units are supplied with the same operands, and in the second operating mode different operands are supplied to both execution units, and both execution units are controlled by the same control signals for the processing of the operands in the first operating mode, and both execution units are controlled by different control signals for the processing of the operands in the second operating mode.

Abstract: A method and a device for delaying the accesses to data and/or instructions of a multiprocessor system having a first and a second processor, with which a memory unit is associated, wherein the second processor operates with a clock pulse offset, and the device is arranged so that the first processor accesses the memory unit and the second processor receives the data and/or instructions with a clock pulse offset.

Abstract: A delay unit and a method for delaying accesses to data and/or instructions of a two-computer system having a first and a second computer, the first and the second computer operating with a time offset, and the delay unit being embodied in such a way that that time offset is compensated for in the two-computer system in the context of the accesses to data and/or instructions in at least one of the two computers, as well as a method and delay unit for delaying accesses to data and/or instructions of a computer system having error discovery mechanisms for error detection, wherein the time span between undelayed access to data and/or instructions and error detection is compensated for.

Abstract: A method for error detection in a cache memory for storing data, the access to the data stored in the cache memory taking place by addresses assigned to them, wherein for the addresses assigned to the stored data, at least one first test signature made up of at least one first signature bit is generated and also stored in the cache memory.

Abstract: A method and a device are described for switching between at least two operating modes of a processor unit including at least two execution units for running programs, at least one identifier being assigned to at least the programs which differentiates between the at least two operating modes, and switching between the operating modes is performed as a function of the identifier such that the processor unit runs the programs according to the assigned operating mode.

Abstract: A program-controlled unit includes a single controller core that has a first and at least a second execution unit, which units are operable independently of one another in a first operating mode, and process the same instructions in parallel in a second operating mode.

Abstract: A method and a device for correcting errors in a processor having two execution units as well as a corresponding processor, in which registers are provided in which instructions and/or associated information can be stored, the instructions being processed redundantly in both execution units and comparison means being included, and being such that by comparing the instructions and/or the associated information a deviation and thus an error is detected, a division of the registers of the processor into first registers and second registers being provided, the first registers being such that a specifiable state of the processor and contents of the second registers are derivable from them, means for a rollback being included, which are such that at least one instruction and/or the information in the first registers are rolled back and are executed anew and/or restored.

Abstract: lkjsdf A system and method for comparing binary data words are provided, which method includes splitting a first and a second data word (A, B) to be compared to one another into at least two subwords, one having high-order bits (hA, hB) and the other having low-order bits (nA, nB), and separately comparing each pair of the corresponding two subwords (hA, hB; nA, nB) in a separate comparing device. The intermediate comparison results of the comparing devices are gated in a logic device, e.g., an AND gate, to yield an overall result as a function of a control signal which is applied to a correction device, which is connected between at least one of the comparing devices and the logic device.