Abstract: A programmable modulator (100) is programmable to operate in either of a GMSK or 8PSK mode. When operating in a GMSK mode, a signal modulating circuit 105 receives (210) a bit stream (110), maps the bit stream (110) to a phase value in complex I, Q form and applies a progressive rotation to the phase value according to GMSK specifications. The output (140) is filtered by a filter circuit (135), preferably using a complex Finite Impulse Response (FIR) filter using the standard coefficients for an 8PSK modulation to create (215) an approximate GMSK output (165). A GMSK correction circuit (150) determines a correction term that is added to the filter circuit output (165) so as to correct amplitude variations to allow the output to conform to GSM/EDGE standards. The same modulator (100) may be programmed to operate in an 8PSK mode with linear predistortion.

Abstract: A filter co-processor within a Digital Signal Processor (DSP) takes advantage of the orthogonal nature of modulated signals during the equalization process. Since, after reception, only certain real/imaginary values of the received signal are useful for demodulation, the filter co-processor only processes those values to estimate the transmitted signal. By processing only those values useful for demodulation, the filter co-processor is able to process more information in a given amount of time, leading to increased processing when compared to the prior art.