Abstract: A detector circuit for detecting an external manipulation of an electrical circuit. The detector circuit includes a digital circuit which is sensitive to at least one of the effects of ionizing radiation or fluctuations of a supply voltage, and the output state of the digital circuit is indicative of an attack.

Abstract: An integrated circuit having a first circuit unit, which is put into a power-saving mode by a control apparatus and into a predetermined initial state when changing from the power-saving mode to a regular operating state. A second circuit unit is put into a power-saving mode by the control apparatus, during which the second circuit unit buffer-stores data and/or instructions adopted immediately prior to the power-saving state, with the second circuit unit resuming and providing the data and/or instructions when changing from the power-saving mode to the regular operating state. The second circuit unit has an input connection to which a first potential is applied in order to change to the power-saving mode and during the power-saving mode, and to which a second potential is applied in order to change to the operating state and during the operating state.

Abstract: An integrated circuit having cascade-connected multiplexers and a precharge unit. The cascade-connected multiplexers each have a plurality of data inputs, a data output, wherein each data input and each data output has two terminals for the application of a dual-rail signal, and a control input, wherein a signal present at the control input defines which of the data inputs is connected to the data output. The precharge unit, which is driven with a precharge unit control signal, is connected to the data output or at least one of the data inputs of one of the multiplexers to thereby bring the data outputs and/or data inputs of the multiplexers into a precharge state before execution of a computation operation.

Abstract: A data processing apparatus having a dual rail circuit component and a control unit for production of drive signals for the dual rail circuit component. The control unit receives an operating mode selection signal, and drive signals for the connected dual rail circuit component are produced as a function of the operating mode selection signal. The circuit components are operated in a security mode or in a power saving mode as a function of the drive signals, with security measures being deactivated in the power saving mode.

Abstract: A decryption circuit for generating a decrypted data signal and a complementary decrypted data signal from a key. In addition, a means for performing a linkage specification so as to generate the logic signal and the complementary logic signal from the decrypted data signal and the complementary decrypted data signal in accordance with the linkage specification. In addition, an encryption means for generating an encrypted logic signal from the key and from the logic signal.

Abstract: Key management device for electronic memories and a method for the encrypted storage of digital data words in electronic memories, in which each stored data word is encrypted with a digital keyword, which may be different from another digital keyword of another stored data word.

Abstract: Circuit arrangement for producing a dual-rail output signal having a signal processing apparatus with two switches, which are driven as a function of an input signal, a first output connected via one of the switches to a signal processing apparatus foot point, which is at a first potential, and a second output connected via the other switch to the foot point. The signal processing apparatus is connected via a switching apparatus to outputs of the circuit arrangement in order to output a dual-rail output signal. The outputs of the switching apparatus are each connected to one or to both inputs of the switching apparatus as a function of a control signal. A potential monitoring apparatus defines the potentials at the outputs of the circuit arrangement when these outputs are not connected via the switching apparatus and the signal processing apparatus to the foot point of the signal processing apparatus.

Abstract: Method for protected transmission of data words includes providing a first data word, transforming the first data word into a sequence including at least one second data word using a first transformation rule, transforming at least one of the second data words into a third data word using a second transformation rule, and checking whether a prescribed relationship exists between the third data word and a comparison data word.

Abstract: A detector circuit for detecting an external manipulation of an electrical circuit. The detector circuit includes a digital circuit which is sensitive to at least one of the effects of ionizing radiation or fluctuations of a supply voltage, and the output state of the digital circuit is indicative of an attack.

Abstract: Circuit arrangement having complementary data input nodes for reception of a dual rail data signal and complementary data output nodes for outputting a dual rail data signal. A connection switch is connected to complementary data nodes by means of which the complementary data nodes can be connected to one another with a low resistance, a control unit is provided for generating a first control signal for the connection switch, and the circuit arrangement is designed to be operated in two operating modes, in which case in a power saving mode, the connection switch is switched by the control unit to have a high resistance, and in a security node, the connection switch is switched by the control unit to have a low resistance when the potential at the complementary data nodes is intended to be equalized.

Abstract: Circuit having a bus, a first receiver circuit part coupled to the bus for processing a signal on the bus, a second receiver circuit part coupled to the bus for processing a signal on the bus, a transmitter circuit part coupled to the bus for outputting a signal on the bus, and a unit for preventing processing a signal on the bus by the first receiver circuit part in response to a control signal.

Abstract: Method for synchronizing a cache memory with a main memory, the cache memory provided to buffer-store data between a processor and the main memory, and memory entries of the cache memory each having a data area and an identification area. The processor provides a synchronization value to determine which memory entries of the data area are to be synchronized with the main memory. A cache logic circuit of the cache memory then compares the synchronization value with contents of a memory field of each memory entry. When there is a match, the cache logic circuit checks a flag of a third memory field of the identification area for a first state, which indicates that a change was made to the data area of the memory entry since the last synchronization. When the flag is in the first state, the contents of the data area are transferred to the main memory.

Abstract: An integrated circuit having at least one line pair to which a dual-rail signal is applied, a switching device, which is connected to the at least one line pair, is controlled by a signal applied to a control connection and is used to transmit the dual-rail signal, which has been applied to the line pair, to an additional line pair, and a memory cell, which is connected to the additional line pair and to a supply potential connection via a controllable switch.

Abstract: The present invention provides a CAM (content addressable memory) apparatus having: a first memory device (10) with a word line input (WL) and at least one storage node (12; 13) for storing a first bit of a data word; a second memory device (11) with a word line input (WL) and at least one storage node (14; 15) for storing a second bit of a data word; and a comparator device (16) for comparing the first and second stored bits with two precoded comparison bits fed via four inputs (20; 21; 22; 23) and for driving a hit node (17) in the event of the first stored bit corresponding to the first comparison bit and the second stored bit corresponding to the second comparison bit.

Abstract: Circuit arrangement having complementary data input nodes for reception of a dual rail data signal and complementary data output nodes for outputting a dual rail data signal. A connection switch is connected to complementary data nodes by means of which the complementary data nodes can be connected to one another with a low resistance, a control unit is provided for generating a first control signal for the connection switch, and the circuit arrangement is designed to be operated in two operating modes, in which case in a power saving mode, the connection switch is switched by the control unit to have a high resistance, and in a security node, the connection switch is switched by the control unit to have a low resistance when the potential at the complementary data nodes is intended to be equalized.

Abstract: Integrated circuit having an intermediate memory area, which has a first part designed to store a data word as an original, and has an at least second part designed to store the data word as a duplicate, and a comparison unit, which is designed to output an alarm signal if the original data word and the at least one duplicate data word do not match.

Abstract: An integrated circuit having a first circuit unit, which is put into a power-saving mode by a control apparatus and into a predetermined initial state when changing from the power-saving mode to a regular operating state. A second circuit unit is put into a power-saving mode by the control apparatus, during which the second circuit unit buffer-stores data and/or instructions adopted immediately prior to the power-saving state, with the second circuit unit resuming and providing the data and/or instructions when changing from the power-saving mode to the regular operating state. The second circuit unit has an input connection to which a first potential is applied in order to change to the power-saving mode and during the power-saving mode, and to which a second potential is applied in order to change to the operating state and during the operating state.

Abstract: One embodiment provides a content addressable memory cell having a first memory cell which is electrically connected to a comparator unit. The comparator unit is constructed from at least eight transistors, at least four transistors being arranged in a first circuit part and at least four transistors being arranged in a second circuit part and each of the circuit parts having at least two circuit branches.

Abstract: A data processing apparatus having a dual rail circuit component and a control unit for production of drive signals for the dual rail circuit component. The control unit receives an operating mode selection signal, and drive signals for the connected dual rail circuit component are produced as a function of the operating mode selection signal. The circuit components are operated in a security mode or in a power saving mode as a function of the drive signals, with security measures being deactivated in the power saving mode.

Abstract: A decryption circuit for generating a decrypted data signal and a complementary decrypted data signal from a key. In addition, a means for performing a linkage specification so as to generate the logic signal and the complementary logic signal from the decrypted data signal and the complementary decrypted data signal in accordance with the linkage specification. In addition, an encryption means for generating an encrypted logic signal from the key and from the logic signal.