Abstract: The application refers to a semiconductor device including: a semiconductor body having a first surface and a second surface; an active region having at least one semiconductor cell configured to conduct a load current between the first surface and the second surface; an edge termination region separating the active region from a chip edge; and a first layer within at least a part of the edge termination region. The first layer includes silicon, nitrogen and hydrogen. In atomic numbers, a ratio of the silicon to the nitrogen is at least 3.3 to 4 in at least a portion of the first layer. At least the portion of the first layer includes at most 16 percent hydrogen in atomic numbers.

Abstract: An IGBT includes a drift region of a first conductivity type, a plurality of trenches laterally confining both first type mesas having a respective source region and a respective body region and second type mesas. A shield region does for example not laterally overlap with the second type mesa, but only with the first type mesa.

Abstract: A power semiconductor device having a power semiconductor transistor configuration includes: a semiconductor body having a front side coupled to a first load terminal structure, a backside coupled to a second load terminal structure, and a lateral chip edge; an active region for conducting a load current in a conducting state; and an edge termination region separating the active region and lateral chip edge. At the front-side, the edge termination region includes a protection region devoid of any metallic structure, unless the metallic structure is electrically shielded from below by a polysilicon layer that extends further towards the lateral chip edge than the metallic structure by a lateral distance of at least 20 ?m. In a blocking state, the protection region accommodates a voltage change of at least 90% of a blocking voltage inside the semiconductor body in a lateral direction from the active region towards the lateral chip edge.

Abstract: A power semiconductor device having a power semiconductor transistor configuration includes: a semiconductor body having a front side coupled to a first load terminal structure, a backside coupled to a second load terminal structure, and a lateral chip edge; an active region for conducting a load current in a conducting state; and an edge termination region separating the active region and lateral chip edge. At the front-side, the edge termination region includes a protection region devoid of any metallic structure, unless the metallic structure is electrically shielded from below by a polysilicon layer that extends further towards the lateral chip edge than the metallic structure by a lateral distance of at least 20 ?m. In a blocking state, the protection region accommodates a voltage change of at least 90% of a blocking voltage inside the semiconductor body in a lateral direction from the active region towards the lateral chip edge.

Abstract: A system including a movable lance (1), which measures or influences physical or chemical quantities of a melt (2) in a converter (3), and a device for contactless position measurement of the movable lance (1). Also, a converter system including such a system and a method for the contactless position measurement of the movable lance (1). For position measurement of a movable lance (1) in converter steel production, the system has a stationary transmitter (4) for emitting electromagnetic waves (7), a stationary receiver (5) for receiving the emitted electromagnetic waves (7), a reflector (6), which is connected to the movable lance (1) and on which the electromagnetic waves (7) can be reflected, and a calculator (8) for calculating the absolute position of the lance from the propagation time of the electromagnetic waves (7) emitted by the transmitter (4) in the direction of the reflector (6), reflected by the reflector (6) in the direction (2) of the receiver means (5), and received by the receiver (5).