Abstract: A surface capacitance sensor system is implemented as an array of sensor electrodes near the surface of the integrated circuit and an array of stimulus electrodes below the sensor electrodes. Rows of stimulus electrodes are driven by sources while the voltages at the respective sensor electrodes are measured. Voltage measurements at each sensor electrode allow the surface capacitance at each sensor electrode location to be determined. The capacitance data is used to determine the positions of target electrodes above the array surface as required in the location fingerprint artifacts.

Abstract: A capacitance sensor system and method includes a capacitive sensor as an array of sensor electrodes near the surface of the integrated circuit and charge pump circuits for measuring the capacitance at each sensor electrode. Shield electrodes and unused sense electrodes are used for background capacitance cancellation at each array location. The shield electrodes are switched between the circuit supply potentials in a manner synchronous to the capacitance sensing at the sense electrodes. The improved background capacitance cancellation allows all circuitry to be located outside the sensor array. The capacitance data is used to determine the positions of fingerprint artifacts and other fingerprint features.

Abstract: An ultra-rugged biometric integrated circuit sensor and method for constructing the same is provided. The sensor comprises a sensing area and a control electronics area, and, as result of its construction, the sensor has a topology whereby the sensing area is elevated with respect to the control electronics area. In other words, a depression is created on the sensor surface that allows the control electronics to escape damaging impacts by external forces. According to one embodiment, the sensing area and control electronics area are structures such there is no overlap between either area, except where the sensing area is electrically coupled to the control electronics. According to another embodiment, the sensor further comprises a electric static discharge structure that creates a least resistant path to ground. The electric static discharge structure further protects the control electronics from high voltage surges encountered in normal operation.

Abstract: A surface capacitance sensor system is implemented as an array of sensor electrodes near the surface of the integrated circuit and an array of stimulus electrodes below the sensor electrodes. Rows of stimulus electrodes are driven by sources while the voltages at the respective sensor electrodes are measured. Voltage measurements at each sensor electrode allow the surface capacitance at each sensor electrode location to be determined. The capacitance data is used to determine the positions of target electrodes above the array surface as required in the location fingerprint artifacts.

Abstract: A capacitance sensor system and method includes a capacitive sensor as an array of sensor electrodes near the surface of the integrated circuit and charge pump circuits for measuring the capacitance at each sensor electrode. Shield electrodes and unused sense electrodes are used for background capacitance cancellation at each array location. The shield electrodes are switched between the circuit supply potentials in a manner synchronous to the capacitance sensing at the sense electrodes. The improved background capacitance cancellation allows all circuitry to be located outside the sensor array. The capacitance data is used to determine the positions of fingerprint artifacts and other fingerprint features.

Abstract: An improved connection assembly for an integrated circuit sensor uses direct chip attachment to connect a circuit board directly to the integrated circuit. The circuit board covers and protects the integrated circuit except over the sensor areas. The use of a thin circuit board reduces the physical interference between the circuit board and the sensor area.

Abstract: A fabrication process for a gallium arsenide MESFET device is disclosed. A feature of the invention is placing a gate structure on the gallium arsenide substrate. Then a process including molecular beam epitaxy, grows epitaxial gallium arsenide on each respective side of the gate, forming a raised source region and a raised drain region. Gallium arsenide will not grow in a conductive state on top of a tungsten gate metal. The resulting MESFET device has a raised source and drain which significantly reduces the high resistance depleted surface adjacent to the gate which generally occurs in planer gallium arsenide MESFET devices. Furthermore, the MESFET channel region which is defined by the proximate edges of the source and the drain, is self-aligned with the edges of the gate by virtue of the insitu process for the formation of the source and drain, as described above.

Abstract: A logic gate is disclosed employing enhancement mode MESFET gallium arsenide devices which do not require the tight process control necessary in the prior art because two such devices are employed in the gate circuit to mutually compensate for the effects of their equal deviation from nominal threshold voltages.