Abstract: A chopper-stabilized amplifier includes a main signal path having first and second chopping circuits at the inputs and outputs of a transconductance amplifier, and an auto-correction feedback loop. The feedback loop includes a transconductance amplifier connected to amplify the chopped output from the main signal path, a third chopping circuit which chops the amplified output, a filter which filters the chopped output to substantially reduce any offset voltage-induced AC component present in the signal being filtered, and a transconductance amplifier which receives the filtered output and produces an output which is coupled back into the main signal path. When properly arranged, the auto-correction feedback loop operates to suppress transconductance amplifier-related offset voltages and offset voltage-induced ripple that might otherwise be present in the amplifier's output.

Abstract: An amplifier front-end comprises an input node for receiving a common-mode voltage Vcm, a differential transistor pair having first and second inputs and outputs, a capacitor, a reference voltage Vref, an error correction circuit, and a switching network. The switching network charges the capacitor to Vref; couples the capacitor to the differential pair's first input and couples Vref to the pair's second input such that the voltage at both inputs is ˜Vref; and couples the input node to the capacitor's other terminal such that the voltage at the first input is level-shifted to ˜(Vcm+Vref). The error correction circuit—typically an auto-zero circuit—is coupled to the differential pair's outputs and arranged to reduce charge injection error and kT/C noise components that would otherwise be present in the outputs due to the level shift.

Abstract: A chopper-stabilized amplifier includes a main signal path having first and second chopping circuits at the inputs and outputs of a transconductance amplifier, and an auto-correction feedback loop. The feedback loop includes a transconductance amplifier connected to amplify the chopped output from the main signal path, a third chopping circuit which chops the amplified output, a filter which filters the chopped output to substantially reduce any offset voltage-induced AC component present in the signal being filtered, and a transconductance amplifier which receives the filtered output and produces an output which is coupled back into the main signal path. When properly arranged, the auto-correction feedback loop operates to suppress transconductance amplifier-related offset voltages and offset voltage-induced ripple that might otherwise be present in the amplifier's output.

Abstract: An amplifier front-end comprises an input node for receiving a common-mode voltage Vcm, a differential transistor pair having first and second inputs and outputs, a capacitor, a reference voltage Vref, an error correction circuit, and a switching network. The switching network charges the capacitor to Vref; couples the capacitor to the differential pair's first input and couples Vref to the pair's second input such that the voltage at both inputs is ˜Vref; and couples the input node to the capacitor's other terminal such that the voltage at the first input is level-shifted to ˜(Vcm+Vref). The error correction circuit—typically an auto-zero circuit—is coupled to the differential pair's outputs and arranged to reduce charge injection error and kT/C noise components that would otherwise be present in the outputs due to the level shift.

Abstract: A current-mode instrumentation amplifier (IA) error reduction circuit and method employs a current-mode IA topology and an auto-zero circuit. The IA receives a differential voltage (VINP?VINN) and produces differential DC currents (IDC1, IDC2) in response, which are summed to produce the amplifier's output current. Ideally, when VINP=VINN, IDC1 and IDC2 will be equal; however, due to mismatches an error component Ierror will be present such that IDC1=IDC2±Ierror. The auto-zero circuit is employed to reduce the magnitude of Ierror. In operation, in an ‘auto-zero mode’, VINP and VINN are connected together and the auto-zero circuit operates to make IDC1=IDC2; a voltage needed to effect this is stored. Then, in ‘normal mode’, VINP and VINN are disconnected from each other and the IA is placed in the signal path, with the stored voltage acting to keep the magnitude of Ierror low.

Abstract: An amplifier topology includes an input stage comprising a differential pair which conducts respective output currents in response to a differential input signal. Bias current sources provide the pair's tail current and respective bias currents for the input stage in response to a drive voltage. After flowing through the input stage, most or all of the input stage bias currents are summed at a summing node, the summed currents being a current Isum. The input stage also has a feedback loop which includes a bias generator circuit arranged to receive Isum, and to provide the drive voltage to the bias current sources such that Isum is maintained approximately constant. By so doing, the output impedance of the bias current sources is effectively increased, which serves to improve the amplifier's CMR and PSR characteristics.

Abstract: An amplifier topology includes an input stage comprising a differential pair which conducts respective output currents in response to a differential input signal. Bias current sources provide the pair's tail current and respective bias currents for the input stage in response to a drive voltage. After flowing through the input stage, most or all of the input stage bias currents are summed at a summing node, the summed currents being a current Isum. The input stage also has a feedback loop which includes a bias generator circuit arranged to receive Isum, and to provide the drive voltage to the bias current sources such that Isum is maintained approximately constant. By so doing, the output impedance of the bias current sources is effectively increased, which serves to improve the amplifier's CMR and PSR characteristics.

Abstract: A ripple current reduction circuit includes a supply node coupled to the output of a high ripple voltage source such as a charge pump. A first current mirror is referred to the supply node and mirrors a current I1 to a second node, the mirrored current (I3) including a ripple current induced by the ripple voltage. A second current mirror is referred to the second node and mirrors a current I2 to an output node, which provides a current ILOAD to a load. The mirrors are sized such that the current provided at the second node is greater than the current required by the second mirror to provide ILOAD. The excess current, at least a portion of which includes a ripple component induced by the ripple voltage, is shunted to ground. As such, the magnitude of the ripple component in ILOAD is less than that present in I3.

Abstract: A ripple current reduction circuit includes a supply node coupled to the output of a high ripple voltage source such as a charge pump. A first current mirror is referred to the supply node and mirrors a current I1 to a second node, the mirrored current (I3) including a ripple current induced by the ripple voltage. A second current mirror is referred to the second node and mirrors a current I2 to an output node, which provides a current ILOAD to a load. The mirrors are sized such that the current provided at the second node is greater than the current required by the second mirror to provide ILOAD. The excess current, at least a portion of which includes a ripple component induced by the ripple voltage, is shunted to ground. As such, the magnitude of the ripple component in ILOAD is less than that present in I3.

Abstract: A chopper-stabilized current-mode instrumentation amplifier comprises first and second input amplifiers coupled to respective input nodes and arranged to produce respective currents in response to a differential input voltage applied to the input nodes; the currents are coupled to an output node. To reduce gain errors that might otherwise arise due to the parasitic capacitances of the on- and/or off-chip devices and/or structures making up the input amplifiers, the invention includes gain correction circuitry coupled to the IA. The gain correction circuitry replicates at least some of the parasitic capacitances, and provides compensation currents to the IA which reduce both input- and output-referred gain errors that might otherwise arise.

Abstract: A current-mode instrumentation amplifier (IA) includes first and second buffer amplifiers which receive a differential voltage (VINP?VINN) and provide output voltages at respective output nodes; a resistance R1 is connected between the nodes and conducts a current IR1 that varies with VINP?VINN. In one embodiment, each amplifier includes a transistor connected in series with R1 which conducts current IR1; these currents are coupled to the input and output terminals of a current mirror, preferably via respective virtual ground nodes such that the IA requires only one current mirror, to produce the IA's output voltage. To minimize DC mismatch errors, the IA is chopper-stabilized, with the buffer amplifiers and signal current paths chopped using a two-phase chopping cycle.

Abstract: A chopper-stabilized current mirror includes a pair of FETs connected to mirror an input current Iin. In one embodiment, switching networks S1 and S2 have their respective inputs connected to the FETs' drains, and are operated with clock signals CLK1 and CLK2, respectively. An ro boost amplifier A1 has its inputs connected to the outputs of S2 and its outputs connected to the gates of a pair of cascode FETs via a switching network S3 which is operated with clock signal CLK2S, with the drain of one cascode FET connected to Iin and the drain of the other providing the mirror's output Iout. S1 is clocked to reduce mismatch errors and S2 and S3 are clocked to reduce errors due to A1's offset voltage, with CLK2 and CLK2S shifted with respect to CLK1 to reduce errors due to parasitic capacitances.

Abstract: A charge pump circuit is configured for charging of parasitic capacitances associated with charge pump capacitors in a manner that minimizes voltage ripple. The charge pump circuit is suitably configured with an independent charging circuit configured for supplying the current needed to charge the parasitic capacitances, rather than utilizing the reservoir capacitor to supply the needed current. The independent charging circuit can be implemented with various configurations of charge pump circuits, such as single phase or dual phase charge pumps, and/or doubler, tripler or inverter configurations. The independent charging circuit includes a parasitic charging capacitor or other voltage source configured with one or more switch devices configured to facilitate charging of the parasitics during any phases of operation of the charge pump circuit.

Abstract: A circuit is provided that can provide, in a single package, a circuit to monitor a sensing element which uses a variable resistor. The circuit (also known as a signal conditioning circuit) may contain resistor input terminals to which a reference set resistor and a resistive sensor can be attached. A reference voltage signal can be applied to both terminals. There are also a circuit for sensing the resulting current flowing through both the set resistor and the resistive sensor. The difference of the currents flowing through each element can then be monitored as being indicative of the difference in resistance between the set resistor and the resistive sensor. The current difference signal can be used to generate a voltage difference signal indicative of the difference in resistance between the set resistor and the resistive sensor. The signal conditioning circuit may be used to adjust the temperature of various devices.

Abstract: A composite loop compensation circuit and method for a low drop-out regulator configured to facilitate stable operation at very low output load currents is provided. An exemplary low drop-out regulator includes an error amplifier, a pass device, and a composite loop compensation circuit. The compensation loop compensation circuit includes a plurality of segmented sense devices, a plurality of switches and a biasing component. The plurality of segmented sense devices are configured to sense an output load current, i.e., the current from the output terminal of the pass device. The plurality of switches are coupled between the plurality of segmented sense devices and a biasing component. Composite loop compensation circuit is configured to adjust the dominant first pole of the composite feedback loop based on the output load current through biasing of the active resistor component.

Abstract: A charge pump circuit is configured for continuous control of the output of the charge pump circuit through continuous use of at least one charge pump capacitor coupled with a servo amplifier. During and between both phases of operation of the charge pump circuit, the output current from the servo amplifier can be set equal to the load current through a continuous path. This servo amplifier configuration facilitates the continuous regulation of the load current, during both phases of operation, as well as in between the phases, and as a result no load current is drawn from the output capacitor, thus requiring no recharge of the output capacitor. In addition, an exemplary charge pump circuit can be configured with level-shifting capabilities, the ability to facilitate the use of lower voltage processes, and the ability to provide a large DC open loop gain and high stability. In addition, an exemplary charge pump circuit can be configured with capabilities for buck/boost operation.

Abstract: A nulling amplifier (52A) for an auto-zeroed amplifier includes a first differential stage including first (3) and second (16) input transistors and a second differential stage including first (18) and second (19) nulling transistors coupled to drains of the second and first input transistors and to a folded cascode circuit (48) coupled to an output stage (59). A gain boost circuit increases the output impedance of the nulling amplifier. The gm ratios of the first and second input transistors and the first and second nulling transistors have values which establish a predetermined low input-referred noise level in the nulling amplifier, and the gain boost circuit maintains a low offset voltage.

Abstract: A current mirror configuration can be integrated in the output stage of an operational amplifier that enables rail-to-rail performance without requiring a significant increase in headroom. The operational amplifier can be configured with a chopper stabilized current mirror configured within the output stage of the operational amplifier. Through use of the integrated current mirror in the output stage of the amplifier, the substrate of the integrated circuit can be suitably grounded to minimize noise problems. To obtain rail-to-rail output performance, the operational amplifier can incorporate a positive and negative charge pump. However, rather than requiring the negative charge pump to charge pump the operational amplifier negative for a full VGS voltage, such as in a conventional current mirror, the integrated current mirror requires minimal headroom for implementation with the operational amplifier.

Abstract: An improved circuit and technique are provided that facilitate residual offset correction during chopper stabilization of an amplifier circuit. A chopper stabilized amplifier can be configured with an additional gain stage configured between input and following stages of the amplifier. Instead of a second switching block being configured on the output of the input stage, the second switching block is coupled to the output of the additional gain stage. As a result, the offset voltage of the additional gain stage appears across the output of the input stage in the same polarity during chopper stabilization. Thus, the offset voltage that appears across the output of the input stage remains constant at the end of each of the chopping phases. Accordingly, any residual offset voltage, for example that due to changes in voltage across parasitic capacitances on the output of the input stage, can be eliminated.

Abstract: A current mirror configuration can be integrated in the output stage of an operational amplifier that enables rail-to-rail performance without requiring a significant increase in headroom. The operational amplifier can be configured with a chopper stabilized current mirror configured within the output stage of the operational amplifier. Through use of the integrated current mirror in the output stage of the amplifier, the substrate of the integrated circuit can be suitably grounded to minimize noise problems. To obtain rail-to-rail output performance, the operational amplifier can incorporate a positive and negative charge pump. However, rather than requiring the negative charge pump to charge pump the operational amplifier negative for a full VGS voltage, such as in a conventional current mirror, the integrated current mirror requires minimal headroom for implementation with the operational amplifier.