Abstract: A data structure contains sequence number metadata which identifies an input/output (I/O) operation such as a full stripe write on a redundant array of independent disks (RAID) mass storage system, and also contains revision number metadata which identifies a subsequent I/O operation such as a read modify write on only a fractional component of the entire user data. The sequence number and revision number metadata are used in an error detection and correction technique, along with parity metadata, to detect and correct silent errors arising from inadvertent data path and drive data corruption. An error to a portion of the stripe is detected by a difference in sequence numbers for all of the components of data. An error arising after an I/O operation is detected by a revision number which is different from the correct revision number.

Abstract: Sequence number metadata which identifies an input/output (I/O) operation, such as a full stripe write on a redundant array of independent disks (RAID) mass storage system, and revision number metadata which identifies an I/O operation such as a read modify write operation on user data recorded in components of the stripe, are used in an error detection and correction technique, along with parity metadata, to detect and correct silent errors arising from inadvertent data path and drive data corruption. An error arising after a full stripe write is detected by a difference in sequence numbers for all of the components of user data in the stripe. An error arising after a read modify write is detected by a revision number which occurred before the correct revision number.

Abstract: Data consistency is verified between geographically separated and connected active and mirroring data processing systems by creating metadata which describes user data, such as a cyclical redundancy code (CRC), and time stamp information which describes the time at which user data was first stored on the active system. The metadata and the time stamp information sent from the active system is compared at the mirroring system with the time stamp information and metadata read from the mirroring system. Upon detecting a discrepancy when comparing the metadata from the active and mirroring systems, the user data from the active or mirroring system which is less current temporally, as determined by the time stamp information, is replaced by the user data from the other one of the active or mirroring systems having the more current temporal time stamp information.

Abstract: Apparatus and method for testing of memory locations containing both test data and test check bits are provided. The apparatus includes a memory controller that communicates with memory devices. In a test mode of operation using a test mode control bit, the memory controller receives test data, together with test check bits that have values corresponding to at least some of the values of the test data. The test data and test check bits are written to desired memory locations of the memory devices. The memory controller is involved in a subsequent read of these same memory locations and receives the test data and test check bits from those previously written memory locations. The memory controller determines whether a correspondence exists between the test check bits that were written and the test check bits that were read. Any lack of correspondence is indicative of one or more memory location faults.

Abstract: A boundary-scan circuit method and apparatus for asserting an internal reset signal connected to core logic circuits of an electronic device in order to assure that testing will begin and end in a safe, known logic state. A safe end state is assured even if the system reset signal on an input pin of the electronic device is logically disconnected from the internal reset connection to the core logic, as often occurs in boundary-scan and related testing.

Abstract: A boundary scan test circuit for inclusion into ASIC and or VLSI circuits which does not require any additional pads/pins to support full boundary scan functionality. The invention uses the power and capability of existing address and data buses to transfer test data into the integrated circuit under boundary scan test, and uses the same buses to transfer test results out of the integrated circuit under test to be interpreted by the test processor of the system.

Abstract: A monitor device connected between a pin for connection to the more positive lead of the voltage supply or the less positive voltage of the power supply and the more positive voltage supply conductors or the less positive voltage supply conductors on the integrated circuit substrate. The monitor circuit has a threshold circuit so insignificant perturbations will not trigger the monitor. The monitor circuit also has a reference voltage input such that the same circuit may be used for the more positive side of the power supply, as well as, the less positive side with straightforward modifications. When the monitor circuit detects a significant fault, i.e. one that could falsely switch part of the integrated circuit, it sets a flip-flop to record such an occurrence. The monitor flip-flop cannot be reset by the usual reset signals, in order to prevent it from being cleared by normal diagnostics and error recovery operations.

Abstract: For LSI/VLSI integrated circuits which inherently have an address decoder and a data bus, a scan testing method and apparatus is presented which does not require additional pin connections to be dedicated for scan test implementation. Counter to the Joint Test Action Group approach, the present invention uses additional registers, multiplexers, and decoders in conjunction with the existing buses to provide test access to otherwise embedded layers of logic circuitry, without the addition of a single pin connection to a integrated circuit chip package. Further, since this test method and apparatus uses the data bus and registers just as the rest of the chip, slow and complex d.c. level shifting equipment is not required.

Abstract: A boundary-scan circuit method and apparatus for asserting an internal reset signal connected to core logic circuits of an electronic device in order to assure that testing will begin and end in a safe, known logic state. A safe end state is assured even if the system reset signal on an input pin of the electronic device is logically disconnected from the internal reset connection to the core logic, as often occurs in boundary-scan and related testing.