Patents by Inventor Thomas Labonte

Thomas Labonte has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12566716
    Abstract: Provided are systems, methods, and apparatuses for timestep shared memory multiprocessing based on tracking table mechanisms. In one or more examples, the systems, devices, and methods include determining a first node writes application data to a memory, obtaining a data address of the memory associated with the application data, and generating an index of the data address based on hashing the data address in a hash function. In one or more examples, the systems, devices, and methods include generating a tracking entry based on the first node writing application data to the memory, storing the index and the tracking entry in a bucket of a hash table, and detecting an access violation to the application data based on the tracking entry indicating a node other than the first node modifies the application data.
    Type: Grant
    Filed: July 26, 2024
    Date of Patent: March 3, 2026
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Douglas Joseph, Thomas Labonte
  • Patent number: 12517847
    Abstract: A computer system including a home node having global shared memory and remote nodes configured to access the global shared memory. The home node contains a modification tracker entry and a timestep count entry associated with each cache block. The home node is configured to: set a timestep counter value in the timestep count entry; modify a word in one of the cache blocks in response to a first write operation from one of the remote nodes; set a first modification tracker value in response to the first write operation; modify a word in the one of the cache blocks in response to a second write operation from one of the remote nodes; set a second modification tracker value in response to the second write operation; and perform a violation check in response to a configuration status register value being equal to the timestep counter value.
    Type: Grant
    Filed: October 3, 2024
    Date of Patent: January 6, 2026
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Thomas Labonte, Douglas Joseph, Samantika Sury
  • Publication number: 20250363053
    Abstract: A system and method for cache management. In some embodiments, a system includes: a lower-level cache; a first upper-level cache; and a second upper-level cache, the lower-level cache, the first upper-level cache, and the second upper-level cache being configured: to store first metadata of a cache line, in the first upper-level cache, the first metadata indicating that the cache line is in a partial state, the partial state indicating that at least two words in the cache line are in different permission states.
    Type: Application
    Filed: December 3, 2024
    Publication date: November 27, 2025
    Inventors: Thomas LABONTE, Samantika SURY, Douglas JOSEPH, Alan GARA
  • Publication number: 20250307175
    Abstract: Provided are systems, methods, and apparatuses for timestep shared memory multiprocessing based on tracking table mechanisms. In one or more examples, the systems, devices, and methods include determining a first node writes application data to a memory, obtaining a data address of the memory associated with the application data, and generating an index of the data address based on hashing the data address in a hash function. In one or more examples, the systems, devices, and methods include generating a tracking entry based on the first node writing application data to the memory, storing the index and the tracking entry in a bucket of a hash table, and detecting an access violation to the application data based on the tracking entry indicating a node other than the first node modifies the application data.
    Type: Application
    Filed: July 26, 2024
    Publication date: October 2, 2025
    Inventors: Douglas JOSEPH, Thomas LABONTE
  • Publication number: 20250190377
    Abstract: A computer system including a home node having global shared memory and remote nodes configured to access the global shared memory. The home node contains a modification tracker entry and a timestep count entry associated with each cache block. The home node is configured to: set a timestep counter value in the timestep count entry; modify a word in one of the cache blocks in response to a first write operation from one of the remote nodes; set a first modification tracker value in response to the first write operation; modify a word in the one of the cache blocks in response to a second write operation from one of the remote nodes; set a second modification tracker value in response to the second write operation; and perform a violation check in response to a configuration status register value being equal to the timestep counter value.
    Type: Application
    Filed: October 3, 2024
    Publication date: June 12, 2025
    Inventors: Thomas Labonte, Douglas Joseph, Samantika Sury