Patents by Inventor Thomas Leddy McDevitt
Thomas Leddy McDevitt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9275951Abstract: A method for reducing areas of high field density in an integrated circuit is disclosed. In one embodiment, the method includes forming a first curvilinear wiring structure in a first interconnect layer of an integrated circuit. A second curvilinear wiring structure may be formed in a second interconnect layer of the integrated circuit, such that the first and second curvilinear wiring structures are substantially vertically aligned. The first curvilinear wiring structure may then be electrically connected to the second curvilinear wiring structure. A corresponding apparatus and design structure are also described.Type: GrantFiled: July 18, 2013Date of Patent: March 1, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Felix Patrick Anderson, Thomas Leddy McDevitt, Anthony Kendall Stamper
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Publication number: 20130307158Abstract: A method for reducing areas of high field density in an integrated circuit is disclosed. In one embodiment, the method includes forming a first curvilinear wiring structure in a first interconnect layer of an integrated circuit. A second curvilinear wiring structure may be formed in a second interconnect layer of the integrated circuit, such that the first and second curvilinear wiring structures are substantially vertically aligned. The first curvilinear wiring structure may then be electrically connected to the second curvilinear wiring structure. A corresponding apparatus and design structure are also described.Type: ApplicationFiled: July 18, 2013Publication date: November 21, 2013Applicant: International Business Machines CorporationInventors: Felix Patrick Anderson, Thomas Leddy McDevitt, Anthony Kendall Stamper
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Patent number: 8530970Abstract: A method for reducing areas of high field density in an integrated circuit is disclosed. In one embodiment, the method includes forming a first curvilinear wiring structure in a first interconnect layer of an integrated circuit. A second curvilinear wiring structure may be formed in a second interconnect layer of the integrated circuit, such that the first and second curvilinear wiring structures are substantially vertically aligned. The first curvilinear wiring structure may then be electrically connected to the second curvilinear wiring structure.Type: GrantFiled: April 22, 2009Date of Patent: September 10, 2013Assignee: International Business Machines CorporationInventors: Felix Patrick Anderson, Thomas Leddy McDevitt, Anthony Kendall Stamper
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Patent number: 8137791Abstract: A structure and method of forming the structure. At least one copper wire is formed within a first dielectric layer of a substrate. The top surface of each copper wire and of the first dielectric layer are essentially coplanar. A recess is formed in the first dielectric layer from the top surface of each copper wire to a recess depth less than a thickness of each copper wire within the first dielectric layer such that the recess surrounds a perimeter surface of each copper wire. A capping layer, which is a copper diffusion barrier, is formed in the recess and on the top surface of each copper wire and on the first dielectric layer. A second dielectric layer is formed on the capping layer. The recess depth has a magnitude sufficient to prevent a lateral fail of the capping layer during packaging and/or operation of the substrate.Type: GrantFiled: December 12, 2007Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Felix Patrick Anderson, Jeffrey Peter Gambino, Thomas Leddy McDevitt, Anthony Kendall Stamper
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Patent number: 8129844Abstract: Electronic devices and design structures of electronic devices containing metal silicide layers. The devices include: a thin silicide layer between two dielectric layers, at least one metal wire abutting a less than whole region of the silicide layer and in electrical contact with the silicide layer.Type: GrantFiled: June 20, 2008Date of Patent: March 6, 2012Assignee: International Business Machines CorporationInventors: Felix Patrick Anderson, Zhong-Xiang He, Thomas Leddy McDevitt, Eric Jeffrey White
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Patent number: 8026606Abstract: A structure and a method for forming the same. The structure includes (a) an interlevel dielectric (ILD) layer; (b) a first electrically conductive line and a second electrically conductive line both residing in the ILD layer; (c) a diffusion barrier region residing in the ILD layer. The diffusion barrier region (i) physically isolates, (ii) electrically couples together, and (iii) are in direct physical contact with the first and second electrically conductive lines. The first and second electrically conductive lines each comprises a first electrically conductive material. The diffusion barrier region comprises a second electrically conductive material different from the first electrically conductive material. The diffusion barrier region is adapted to prevent a diffusion of the first electrically conductive material through the diffusion barrier region.Type: GrantFiled: August 25, 2009Date of Patent: September 27, 2011Assignee: International Business Machines CorporationInventors: Stephen Ellinwood Luce, Thomas Leddy McDevitt, Anthony Kendall Stamper
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Publication number: 20090317973Abstract: Electronic devices and design structures of electronic devices containing metal silicide layers. The devices include: a thin silicide layer between two dielectric layers, at least one metal wire abutting a less than whole region of the silicide layer and in electrical contact with the silicide layer.Type: ApplicationFiled: June 20, 2008Publication date: December 24, 2009Inventors: Felix Patrick Anderson, Zhong-Xiang He, Thomas Leddy McDevitt, Eric Jeffrey White
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Publication number: 20090309223Abstract: A structure and a method for forming the same. The structure includes (a) an interlevel dielectric (ILD) layer; (b) a first electrically conductive line and a second electrically conductive line both residing in the ILD layer; (c) a diffusion barrier region residing in the ILD layer. The diffusion barrier region (i) physically isolates, (ii) electrically couples together, and (iii) are in direct physical contact with the first and second electrically conductive lines. The first and second electrically conductive lines each comprises a first electrically conductive material. The diffusion barrier region comprises a second electrically conductive material different from the first electrically conductive material. The diffusion barrier region is adapted to prevent a diffusion of the first electrically conductive material through the diffusion barrier region.Type: ApplicationFiled: August 25, 2009Publication date: December 17, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen Ellinwood Luce, Thomas Leddy McDevitt, Anthony Kendall Stamper
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Patent number: 7585758Abstract: A structure and a method for forming the same. The structure includes (a) an interlevel dielectric (ILD) layer; (b) a first electrically conductive line and a second electrically conductive line both residing in the ILD layer; (c) a diffusion barrier region residing in the ILD layer. The diffusion barrier region (i) physically isolates, (ii) electrically couples together, and (iii) are in direct physical contact with the first and second electrically conductive lines. The first and second electrically conductive lines each comprises a first electrically conductive material. The diffusion barrier region comprises a second electrically conductive material different from the first electrically conductive material. The diffusion barrier region is adapted to prevent a diffusion of the first electrically conductive material through the diffusion barrier region.Type: GrantFiled: November 6, 2006Date of Patent: September 8, 2009Assignee: International Business Machines CorporationInventors: Stephen Ellinwood Luce, Thomas Leddy McDevitt, Anthony Kendall Stamper
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Publication number: 20090155541Abstract: A structure and method of forming the structure. At least one copper wire is formed within a first dielectric layer of a substrate. The top surface of each copper wire and of the first dielectric layer are essentially coplanar. A recess is formed in the first dielectric layer from the top surface of each copper wire to a recess depth less than a thickness of each copper wire within the first dielectric layer such that the recess surrounds a perimeter surface of each copper wire. A capping layer, which is a copper diffusion barrier, is formed in the recess and on the top surface of each copper wire and on the first dielectric layer. A second dielectric layer is formed on the capping layer. The recess depth has a magnitude sufficient to prevent a lateral fail of the capping layer during packaging and/or operation of the substrate.Type: ApplicationFiled: December 12, 2007Publication date: June 18, 2009Inventors: Felix Patrick Anderson, Jeffrey Peter Gambino, Thomas Leddy McDevitt, Anthony Kendall Stamper
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Patent number: 7538006Abstract: A method for forming a vertical natural capacitor in an integrated circuit is disclosed. In one embodiment, the method includes forming a first set of concentric conductive annular structures in a first metal layer of an integrated circuit. The first set includes a first electrode and a second electrode. The method further includes forming a second set of concentric conductive annular structures in a second metal layer of the integrated circuit, the second set being substantially axially concentric with the first set. The second set also includes a first electrode and a second electrode. The method includes coupling, using conductive vias, the first electrode of the first set to the first electrode of the second set, and the second electrode of the first set to the second electrode of the second set.Type: GrantFiled: May 24, 2008Date of Patent: May 26, 2009Assignee: International Business Machines CorporationInventors: Felix Patrick Anderson, Thomas Leddy McDevitt, Anthony Kendall Stamper
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Publication number: 20080105977Abstract: A structure and a method for forming the same. The structure includes (a) an interlevel dielectric (ILD) layer; (b) a first electrically conductive line and a second electrically conductive line both residing in the ILD layer; (c) a diffusion barrier region residing in the ILD layer. The diffusion barrier region (i) physically isolates, (ii) electrically couples together, and (iii) are in direct physical contact with the first and second electrically conductive lines. The first and second electrically conductive lines each comprises a first electrically conductive material. The diffusion barrier region comprises a second electrically conductive material different from the first electrically conductive material. The diffusion barrier region is adapted to prevent a diffusion of the first electrically conductive material through the diffusion barrier region.Type: ApplicationFiled: November 6, 2006Publication date: May 8, 2008Inventors: Stephen Ellinwood Luce, Thomas Leddy McDevitt, Anthony Kendall Stamper
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Patent number: 6333559Abstract: The present invention provides a method for fabricating an integrated circuit (IC) structure having an Al contact in electrical communication with Cu wiring embedded in the initial semiconductor wafer. In accordance with the method of the present invention, the Al contact is formed in areas of the IC structure which contain or do not contain an underlying region of Cu wiring. The present invention also provides a method of interconnecting the fabricated structure to a semiconducting packaging material through the use of a wirebond or Controlled Collapse Chip Connection (C4) solder.Type: GrantFiled: January 19, 2000Date of Patent: December 25, 2001Assignee: International Business Machines CorporationInventors: Gregory Costrini, Ronald Dean Goldblatt, John Edward Heidenreich, III, Thomas Leddy McDevitt
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Patent number: 6187680Abstract: The present invention provides a method for fabricating an integrated circuit (IC) structure having an Al contact in electrical communication with Cu wiring embedded in the initial semiconductor wafer. In accordance with the method of the present invention, the Al contact is formed in areas of the IC structure which contain or do not contain an underlying region of Cu wiring. The present invention also provides a method of interconnecting the fabricated structure to a semiconducting packaging material through the use of a wirebond or Controlled Collapse Chip Connection (C4) solder.Type: GrantFiled: October 7, 1998Date of Patent: February 13, 2001Assignee: International Business Machines CorporationInventors: Gregory Costrini, Ronald Dean Goldblatt, John Edward Heidenreich, III, Thomas Leddy McDevitt