Abstract: Storage protection is provided in a computer system having address translation by loading address translate registers with valid translated addresses and with special addresses. A circuit for generating a storage exception signal is connected to receive all addresses from the translate registers which are addressed by the main storage address and generates a storage exception signal in response to detecting a special address. The address translation mode is provided for both a main storage processor and a control processor with a separate address translate control register for each processor. Address translation is automatically selected based upon interrupt level. Address translation registers are also provided for I/O operations and are controlled independently from and can be in parallel with the task address translation registers.