Abstract: A method includes transferring, by a memory controller from non-volatile memory to volatile memory, a bit sequence comprising video data and control information and transferring, by a first programmable real-time unit (PRU) from the volatile memory to a scratchpad register, the bit sequence. The method also includes transferring, by a second PRU from the scratchpad register to a general purpose input output (GPIO) register, the bit sequence, where the GPIO register is adapted to be coupled to a spatial light modulator (SLM).

Abstract: A receiver which receives a stream of data packets including video data packets over a physical data link and drops data packets when an error on a physical communication layer is detected, wherein the receiver comprises a processor, configured so that it is able to check whether the received data packet is a video packet and whether it is corrupted by an error on the physical communication layer. If this is the case, the video packet is marked as corrupted and forwarded to the network layer. There is further provided a method for processing a stream of data packets including video data packets, the method including checking for each data packet whether it is a video data packet; checking for each video data packet whether it is corrupted by an error on the physical communication layer; marking a video packet as corrupted if it is corrupted due to an error on the physical communication layer; and forwarding the marked corrupted video packet to the network layer.

Abstract: A receiver which receives a stream of data packets including video data packets over a physical data link and drops data packets when an error on a physical communication layer is detected, wherein the receiver comprises a processor, configured so that it is able to check whether the received data packet is a video packet and whether it is corrupted by an error on the physical communication layer. If this is the case, the video packet is marked as corrupted and forwarded to the network layer. There is further provided a method for processing a stream of data packets including video data packets, the method including checking for each data packet whether it is a video data packet; checking for each video data packet whether it is corrupted by an error on the physical communication layer; marking a video packet as corrupted if it is corrupted due to an error on the physical communication layer; and forwarding the marked corrupted video packet to the network layer.

Abstract: An apparatus is provided for configuring data cells received in a telecommunications process in a continuous stream of data cells of fixed length and each comprising a header and a user data part. The apparatus comprises a processing unit, adapted and configured so that it is able to check data cells for the presence of empty cells, discard the data cells consisting of empty cells and then check the user data parts of the data cells less the empty cells—without the need to buffer the same—as to whether they belong together, and then to assemble the user data parts of the data cells belonging together into a frame. The apparatus may be integrated in, a modem and is also particularly suitable for data cells existing as ATM cells for receiving by an ATM system. The invention relates in addition to a correspondingly sequencing method for configuring data cells.

Abstract: An apparatus is provided for configuring data cells received in a telecommunications process in a continuous stream of data cells of fixed length and each comprising a header and a user data part. The apparatus comprises a processing unit, adapted and configured so that it is able to check data cells for the presence of empty cells, discard the data cells consisting of empty cells and then check the user data parts of the data cells less the empty cells—without the need to buffer the same—as to whether they belong together, and then to assemble the user data parts of the data cells belonging together into a frame. The apparatus may be integrated in, a modem and is also particularly suitable for data cells existing as ATM cells for receiving by an ATM system. The invention relates in addition to a correspondingly sequencing method for configuring data cells.

Abstract: A method of resynchronizing data transfer between a first modem assigned to a central office and connected by a dedicated line a second modem assigned to a remote subscriber following a fault caused by a ringing signal. A ringing ID is set up in the central office modem as soon as a ringing signal is to be sent to the subscriber modem, and a ringing alert is transferred to the connected subscriber modem. Transmission of the pilot tone accompanying the data transfer set by the central office modem is interrupted as is the clock frequency synchronization implemented during data transfer in the subscriber modem with the pilot tone as reference. The two modems are put on hold to save the characteristic parameters for the momentary data transfer followed by transfer of the ringing signal via the dedicated line to the subscriber modem.

Abstract: A method of resynchronizing data transfer between two modems connected by a dedicated line following a fault caused by a ringing signal, whereby at least one of the modems is assigned to a central office and the other modem is assigned to a remote subscriber, is implemented by setting a ringing ID in the central office modem as soon as a ringing signal is to be sent to the subscriber modem connected via the dedicated line, transferring a ringing alert to the connected subscriber modem, interrupting transmission of the pilot tone accompanying the data transfer set by the central office modem and interrupting clock frequency synchronization implemented during data transfer in the subscriber modem with the pilot tone as reference, signalling the central office modem and subscriber modem on hold to save the characteristic parameters for the momentary data transfer in the two modems followed by transfer of the ringing signal via the dedicated line to the subscriber modem, resetting the ringing ID in the central of

Abstract: A data processing device includes a data processing core (43), a cache (33) connected to the core and having a cache width, and a bus (31) for receiving from an information source external to the data processing device a burst of information having a width which exceeds the cache width by a width difference. The cache is coupled to the bus to receive and store a first portion of the burst which is equal in width to the cache width. A storage circuit (35) is coupled to the bus to receive and store a second portion of the burst corresponding to the width difference, and the storage circuit has an output coupled to the core.

Abstract: The hit rate of a cache memory (43) is improved by monitoring data transfer commands on a command bus (51) by Non-Cache circuitry (45A). Cache data replacements are inhibited after a consecutive sequence of data transfers which exceeds a threshold number of data transfers are detected by Non-Cache circuitry (45A). The threshold number is selected to be an amount of data transfers which is large enough to imply that a large block of data is being transferred. Such large data blocks tend to flush the cache and reduce subsequent cache hit rate. Other sources of cache inhibit signals may be included, such as System Cache Enable (SKEN), to inhibit caching for other reasons, such as when non-cacheable areas such as video memory are being accessed. Inhibiting useless cache data replacements in this manner improves hit rate and reduces power consumption.

Abstract: A data processing device includes a data processing core (43), a cache (33) connected to the core and having a cache width, and a bus (31) for receiving from an information source external to the data processing device a burst of information having a width which exceeds the cache width by a width difference. The cache is coupled to the bus to receive and store a first portion of the burst which is equal in width to the cache width. A storage circuit (35) is coupled to the bus to receive and store a second portion of the burst corresponding to the width difference, and the storage circuit has an output coupled to the core.