Abstract: The disclosure relates to a method for serially transmitting a frame from a transmitter to at least one receiver via a bus line, as well as a subscriber station for a bus system. According to said method, stuff bits for generating additional signal edges are inserted into the frame by the transmitter according to a predetermined rule, and the stuff bits are removed again by the receiver when evaluating a received frame, a CRC calculation logic of a CRC generator calculating a CRC checksum that is comprised by said frame, and a value of “1” being inserted into said CRC calculation logic in an additional evaluation step if a value of “0 . . . 0” has been determined for the CRC checksum in the running calculation executed by the CRC calculation logic.

Abstract: The disclosure relates to a method for serially transmitting a frame from a transmitter to at least one receiver via a bus line, as well as a subscriber station for a bus system. According to said method, stuff bits for generating additional signal edges are inserted into the frame by the transmitter according to a predetermined rule, and the stuff bits are removed again by the receiver when evaluating a received frame, a CRC calculation logic of a CRC generator calculating a CRC checksum that is comprised by said frame, and a value of “1” being inserted into said CRC calculation logic in an additional evaluation step if a value of “0 . . . 0” has been determined for the CRC checksum in the running calculation executed by the CRC calculation logic.

Abstract: A circuit arrangement for a data processing system is configured to process data in a plurality of modules. The circuit arrangement is configured such that each module is provided with at least one clock pulse, a time base and a base of at least one additional physical variable. The circuit arrangement also comprises a central routing unit to which the plurality of modules are coupled and via which the plurality of modules can periodically exchange data amongst themselves, based on the time base and/or the base of other physical variables. Each module is configured independently and parallel to other modules of the plurality of modules in order to process data. The circuit arrangement is employed in a corresponding method.

Abstract: A method and an apparatus for data transfer in a network having at least two data processing units that exchange messages via the network are described, the exchanged messages having a logical structure in accordance with the CAN specification ISO 11898-1, coding of the bits for at least one first predefinable region within the exchanged messages being accomplished according to the method in accordance with the CAN standard ISO-11898-1, and such that when a switchover condition exists, coding of the bits for at least one second predefinable region within the exchanged messages is accomplished according to a method departing from the CAN standard ISO 11898-1.

Abstract: A method and an apparatus for data transfer in a network having at least two data processing units that exchange messages via the network are described, the exchanged messages having a logical structure in accordance with the CAN specification ISO 11898-1, coding of the bits for at least one first predefinable region within the exchanged messages being accomplished according to the method in accordance with the CAN standard ISO-11898-1, and such that when a switchover condition exists, coding of the bits for at least one second predefinable region within the exchanged messages is accomplished according to a method departing from the CAN standard ISO 11898-1.

Abstract: A circuit arrangement for a data processing system is configured to process data in a plurality of modules. The circuit arrangement is configured such that each module is provided with at least one clock pulse, a time base and a base of at least one additional physical variable. The circuit arrangement also comprises a central routing unit to which the plurality of modules are coupled and via which the plurality of modules can periodically exchange data amongst themselves, based on the time base and/or the base of other physical variables. Each module is configured independently and parallel to other modules of the plurality of modules in order to process data. The circuit arrangement is employed in a corresponding method.

Abstract: A companion chip for a microcontroller has a microprocessor bus domain and a peripheral module bus domain, which are connected to each other via a bus bridge. The microprocessor bus domain includes at least one microprocessor core, and the peripheral module bus domain includes at least one global time-management module as well as modules for communication with the outside world and for signal processing. The companion chip further includes at least one FIFO module for transmitting data within the chip, and between the chip and the microcontroller, and a management module connected to the FIFO module, which ensures the consistency of the data by associating a respective time value and/or an angle of rotation.

Abstract: A companion chip for a microcontroller has a microprocessor bus domain and a peripheral module bus domain, which are connected to each other via a bus bridge. The microprocessor bus domain includes at least one microprocessor core, and the peripheral module bus domain includes at least one global time-management module as well as modules for communication with the outside world and for signal processing. The companion chip further includes at least one FIFO module for transmitting data within the chip, and between the chip and the microcontroller, and a management module connected to the FIFO module, which ensures the consistency of the data by associating a respective time value and/or an angle of rotation.

Abstract: A device for correcting errors in a system having at least two execution units having registers is presented, the registers being designed for recording data. The device has comparison device(s) that are set up such that through a comparison of data that are provided for storage in the registers, a deviation and thus an error may be ascertained. Furthermore, at least one shadow register that is set up such that data concerning the data of the registers may be stored therein, and device(s) are provided for restoring error-free data in at least one register on the basis of the data in the at least one shadow register when an error is detected. This device may be used to improve the safety of a multicore processor.

Abstract: A control unit, for controlling safety-critical applications, includes a microcomputer, a monitoring unit (check unit), and peripheral circuits (input/output), and in which, to improve the reliability of the error detection for such control units, and to expand the detection to additional error types, the monitoring unit includes a first apparatus, arrangement or structure for measuring the quiescent current of the microcomputer; at least one quiescent current handshake line for controlling the measurement of the quiescent current running between the first apparatus, arrangement or structure of the monitoring unit and the microcomputer; the monitoring unit including a second apparatus, arrangement or structure for applying a test data input signal to the microcomputer, for processing the test data input signal, and for comparing the corresponding test data output signal of the microcomputer to the corresponding test data output signal of the monitoring unit; and at least one test data signal transmission line