Patents by Inventor Thomas Lovell Williams

Thomas Lovell Williams has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240120367
    Abstract: An electronic device includes a first dielectric layer above a semiconductor layer, lower-bandgap dielectric layer above the first dielectric layer, the lower-bandgap dielectric layer having a bandgap energy less than a bandgap energy of the first dielectric layer, a first capacitor plate above the lower-bandgap dielectric layer in a first plane of first and second directions, a second dielectric layer above the first capacitor plate, a second capacitor plate above the second dielectric layer in a second plane of the first and second directions, the first and second capacitor plates spaced apart from one another along a third direction, and a conductive third capacitor plate above the second dielectric layer in the second plane, the third capacitor plate spaced apart from the second capacitor plate in the second plane.
    Type: Application
    Filed: December 20, 2023
    Publication date: April 11, 2024
    Inventors: Elizabeth Costner Stewart, Thomas Dyer Bonifield, Jeffrey Alan West, Byron Lovell Williams
  • Publication number: 20240113155
    Abstract: A microelectronic device includes a galvanic isolation component having a lower isolation element over a substrate with lower bond pads connected to the lower isolation element, a dielectric plateau over the lower isolation element that does not extend to the lower bond pads, and an upper isolation element and upper bond pads over the dielectric plateau. The upper bond pads are laterally separated from the lower bond pads by an isolation distance. The microelectronic device includes high voltage wire bonds on the upper bond pads that extend upward, within 10 degrees of vertical, for a vertical distance greater than the isolation distance. The microelectronic device further includes low voltage wire bonds on the lower bond pads that have a loop height directly over a perimeter of the substrate that is less than 5 times a wire diameter of the low voltage wire bonds.
    Type: Application
    Filed: December 27, 2022
    Publication date: April 4, 2024
    Inventors: Jeffrey Alan West, Hung-Yu Chou, Byron Lovell Williams, Thomas Dyer Bonifield
  • Publication number: 20240112953
    Abstract: A microelectronic device including a galvanic isolator with filler metal within an upper isolation element. The galvanic isolator includes a lower isolation element, an upper isolation element, and an inorganic dielectric plateau between the lower isolation element and the upper isolation element. The upper isolation element contains tines of filler metal which are electrically tied to each other and are electrically tied to the upper isolation element. The ends of the tines are rounded to minimize electric fields. The filler metal increases the overall metal density on the metal layer of the upper isolation element to meet the typical metal density requirements of modern microelectronic fabrication processing.
    Type: Application
    Filed: December 29, 2022
    Publication date: April 4, 2024
    Inventors: Jeffrey Alan West, Elizabeth Costner Stewart, Thomas Dyer Bonifield, Byron Lovell Williams, Kashyap Barot, Viresh Chinchansure, Sreeram N S
  • Publication number: 20240113094
    Abstract: A microelectronic device includes a galvanic isolation device on a silicon substrate and a semiconductor device on a semiconductor substrate. The galvanic isolation device includes a lower isolation element over the silicon substrate and an upper isolation element above the lower isolation element, separated by a dielectric plateau that comprises inorganic dielectric material extending from the lower isolation element to the upper isolation element. The galvanic isolation device includes lower bond pads connected to the lower isolation element adjacent to the dielectric plateau, and upper bond pads over the dielectric plateau, connected to the upper isolation element. The semiconductor device includes an active component, and device bond pads coupled to the active component. The microelectronic device includes first electrical connections to the lower bond pads and second electrical connections to the upper bond pads.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Inventors: Jeffrey Alan West, Sreeram N. S., Kashyap Barot, Thomas Dyer Bonifield, Byron Lovell Williams, Elizabeth Costner Stewart
  • Publication number: 20150029153
    Abstract: A device is removeably attachable to a fingertip portion of a glove worn on a hand of a user for use with a touch screen device. The device includes a conductive film layer and an adhesive layer secured to the conductive film layer. The adhesive layer is removeably attachable to the glove, and the conductive film layer is capable of contacting the touch screen device.
    Type: Application
    Filed: October 15, 2014
    Publication date: January 29, 2015
    Inventors: Thomas Lovell Williams, Alex Lawson, Greg Sarmas, SR.
  • Publication number: 20110289654
    Abstract: A device is removeably attachable to a fingertip portion of a glove worn on a hand of a user for use with a touch screen device. The device includes a conductive film layer and an adhesive layer secured to the conductive film layer. The adhesive layer is removeably attachable to the glove, and the conductive film layer is capable of contacting the touch screen device.
    Type: Application
    Filed: May 25, 2011
    Publication date: December 1, 2011
    Inventors: Thomas Lovell Williams, Alex Lawson, Greg Sarmas, SR.