Patents by Inventor Thomas Lovett
Thomas Lovett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11095560Abstract: Technologies for Ethernet gateway congestion management in HPC architectures include a high-performance computing (HPC) switch with an Ethernet gateway that is configured to receive an HPC packet from an HPC fabric via a virtual lane (VL) of the Ethernet gateway. The Ethernet gateway is further configured to determine whether the HPC packet corresponds to a backward error correction notification (BECN), identify one or more priority code points (PCPs) of the HPC packet corresponding to a BECN as a function of the VL on which the HPC packet was received, and generate an Ethernet priority-based flow control (PFC) frame that includes the one or more identified PCPs in a header of the Ethernet PFC frame. Additionally, the Ethernet gateway is configured to transmit the Ethernet PFC frame to an Ethernet fabric as a function of the one or more identified PCPs. Other embodiments are described herein.Type: GrantFiled: December 30, 2017Date of Patent: August 17, 2021Assignee: Intel CorporationInventors: Gary Muntz, Robert Zak, Thomas Lovett, Michael A. Parker
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Patent number: 11063884Abstract: This disclosure describes enhancements to Ethernet for use in higher performance applications like Storage, HPC, and Ethernet based fabric interconnects. This disclosure provides various mechanisms for lossless fabric enhancements with error-detection and retransmissions to improve link reliability, frame pre-emption to allow higher priority traffic over lower priority traffic, virtual channel support for deadlock avoidance by enhancing Class of service functionality defined in IEEE 802.1Q, a new header format for efficient forwarding/routing in the fabric interconnect and header CRC for reliable cut-through forwarding in the fabric interconnect. The enhancements described herein, when added to standard and/or proprietary Ethernet protocols, broadens the applicability of Ethernet to newer usage models and fabric interconnects that are currently served by alternate fabric technologies like Infiniband, Fibre Channel and/or other proprietary technologies, etc.Type: GrantFiled: August 28, 2019Date of Patent: July 13, 2021Assignee: Intel CorporationInventors: Ilango Ganga, Alain Gravel, Thomas Lovett, Radia Perlman, Greg Regnier, Anil Vasudevan, Hugh Wilkinson
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Publication number: 20190386934Abstract: This disclosure describes enhancements to Ethernet for use in higher performance applications like Storage, HPC, and Ethernet based fabric interconnects. This disclosure provides various mechanisms for lossless fabric enhancements with error-detection and retransmissions to improve link reliability, frame pre-emption to allow higher priority traffic over lower priority traffic, virtual channel support for deadlock avoidance by enhancing Class of service functionality defined in IEEE 802.1Q, a new header format for efficient forwarding/routing in the fabric interconnect and header CRC for reliable cut-through forwarding in the fabric interconnect. The enhancements described herein, when added to standard and/or proprietary Ethernet protocols, broadens the applicability of Ethernet to newer usage models and fabric interconnects that are currently served by alternate fabric technologies like Infiniband, Fibre Channel and/or other proprietary technologies, etc.Type: ApplicationFiled: August 28, 2019Publication date: December 19, 2019Applicant: Intel CorporationInventors: Ilango Ganga, Alain Gravel, Thomas Lovett, Radia Perlman, Greg Regnier, Anil Vasudevan, Hugh Wilkinson
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Patent number: 10404625Abstract: This disclosure describes enhancements to Ethernet for use in higher performance applications like Storage, HPC, and Ethernet based fabric interconnects. This disclosure provides various mechanisms for lossless fabric enhancements with error-detection and retransmissions to improve link reliability, frame pre-emption to allow higher priority traffic over lower priority traffic, virtual channel support for deadlock avoidance by enhancing Class of service functionality defined in IEEE 802.1Q, a new header format for efficient forwarding/routing in the fabric interconnect and header CRC for reliable cut-through forwarding in the fabric interconnect. The enhancements described herein, when added to standard and/or proprietary Ethernet protocols, broadens the applicability of Ethernet to newer usage models and fabric interconnects that are currently served by alternate fabric technologies like Infiniband, Fiber Channel and/or other proprietary technologies, etc.Type: GrantFiled: September 25, 2014Date of Patent: September 3, 2019Assignee: Intel CorporationInventors: Ilango Ganga, Alain Gravel, Thomas Lovett, Radia Perlman, Greg Regnier, Anil Vasudevan, Hugh Wilkinson
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Publication number: 20190044864Abstract: Technologies for Ethernet gateway congestion management in HPC architectures include a high-performance computing (HPC) switch with an Ethernet gateway that is configured to receive an HPC packet from an HPC fabric via a virtual lane (VL) of the Ethernet gateway. The Ethernet gateway is further configured to determine whether the HPC packet corresponds to a backward error correction notification (BECN), identify one or more priority code points (PCPs) of the HPC packet corresponding to a BECN as a function of the VL on which the HPC packet was received, and generate an Ethernet priority-based flow control (PFC) frame that includes the one or more identified PCPs in a header of the Ethernet PFC frame. Additionally, the Ethernet gateway is configured to transmit the Ethernet PFC frame to an Ethernet fabric as a function of the one or more identified PCPs. Other embodiments are described herein.Type: ApplicationFiled: December 30, 2017Publication date: February 7, 2019Inventors: Gary Muntz, Robert Zak, Thomas Lovett, Michael A. Parker
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Publication number: 20150117177Abstract: This disclosure describes enhancements to Ethernet for use in higher performance applications like Storage, HPC, and Ethernet based fabric interconnects. This disclosure provides various mechanisms for lossless fabric enhancements with error-detection and retransmissions to improve link reliability, frame pre-emption to allow higher priority traffic over lower priority traffic, virtual channel support for deadlock avoidance by enhancing Class of service functionality defined in IEEE 802.1Q, a new header format for efficient forwarding/routing in the fabric interconnect and header CRC for reliable cut-through forwarding in the fabric interconnect. The enhancements described herein, when added to standard and/or proprietary Ethernet protocols, broadens the applicability of Ethernet to newer usage models and fabric interconnects that are currently served by alternate fabric technologies like Infiniband, Fibre Channel and/or other proprietary technologies, etc.Type: ApplicationFiled: September 25, 2014Publication date: April 30, 2015Inventors: Ilango Ganga, Alain Gravel, Thomas Lovett, Radia Perlman, Greg Regnier, Anil Vasudevan, Hugh Wilkinson
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Publication number: 20050138299Abstract: The management of transactions received by a coherency controller is disclosed. A method of an embodiment of the invention is performed by a coherency controller of a plurality of coherency controllers of a node that has a plurality of sub-nodes. The coherency controller receives a transaction from one of the sub-nodes of the node. The transaction may relate to another sub-node of the node. However, the coherency controller nevertheless processes the transaction without having to send the transaction to another coherency controller of the node, even though the sub-node from which the transaction was received is different than the sub-node to which the transaction relates. The plurality of coherency controllers is thus shared by all of the plurality of sub-nodes of the node.Type: ApplicationFiled: December 18, 2003Publication date: June 23, 2005Inventors: Wayne Downer, Donald DeSota, Thomas Lovett
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Publication number: 20050060383Abstract: The temporary storage of a memory line to be stored in a cache while waiting for another memory line to be evicted from the cache is disclosed. A method includes evicting a first memory line currently stored in the cache and storing a second memory line not currently stored in the cache in its place. While the first memory line is being evicted, such as by first being inserted into an eviction queue, the second memory line is temporarily stored in a buffer. The buffer may be a data transfer buffer (DTB). Upon eviction of the first memory line, the second memory line is moved from the buffer into the cache.Type: ApplicationFiled: September 12, 2003Publication date: March 17, 2005Inventors: Thomas Lovett, Maged Michael, Robert Joersz, Donald DeSota