Patents by Inventor Thomas Ludwig

Thomas Ludwig has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020099194
    Abstract: The present invention provides a nucleic acid molecule comprising: (a) a region of DNA which is homologous to a region of an endogenous gene present in a genome of a cell of interest; (b) a first nucleic acid encoding an encephalomyocarditis internal ribosome entry site (EMCV IRES); (c) a second nucleic acid encoding a selectable marker which can be excised from the nucleic acid molecule if the nucleic acid molecule has been integrated into the genome of the cell of interest; and (d) a third nucleic acid encoding a gene of interest. The cell may be an animal cell, a yeast cell or a plant cell. The invention also provides for transgenic non-human animals which are created using the above described construct. The invention also provides methods for making such transgenic animals.
    Type: Application
    Filed: July 13, 2001
    Publication date: July 25, 2002
    Applicant: The Trustees of Columbia University
    Inventors: Argiris Efstratiadis, Thomas Ludwig, Ana Kljuic, Katerina Politi
  • Patent number: 6240848
    Abstract: A device for firing a pyrotechnic propellent composition having a sensor mass (3) which for firing purposes releases a locking lever (4) which in the rest position bears lockingly against a ring (9) of the firing pin (1).
    Type: Grant
    Filed: August 10, 1998
    Date of Patent: June 5, 2001
    Assignee: Breed Automotive Technology, Inc.
    Inventors: Martin Specht, Thomas Ludwig
  • Patent number: 5944772
    Abstract: A combined adder and logic unit having a reduced operation delay of arithmetic and logic operations, and providing an improved fan in and reduced wiring delays and capacity if implemented in the arithmetic and logic section of a microprocessor chip. The unit comprises a carry network (30) connected to operand inputs for generating carry-out signals of the byte positions (By0-By7) and further comprises a pre-sum logic (32) having a bit function generator (42) and a sum generator (45, 46, 48). Said bit function generator derives from the operands Ai and Bi bit functions Gi, Pi which are provided as logic function output and as input to said sum generator for producing preliminary arithmetic functions (SUM0, SUM1) to anticipate carry-in signals of one or zero.
    Type: Grant
    Filed: November 13, 1997
    Date of Patent: August 31, 1999
    Assignee: International Business Machines Corporation
    Inventors: Juergen Haas, Wilhelm Haller, Ulrich Krauch, Thomas Ludwig, Holger Wetter
  • Patent number: 5934597
    Abstract: A belt retractor with a belt spool rotatably mounted in a frame comprises an integrated force limiter, which has a metal band with a first end connected to the belt spool, and a control part rotatably mounted relative to the belt spool, said control part being able to be locked stationary on the frame by a locking mechanism, said metal band having a second end connected to said control part, said metal band being led through a baffle which is fixed to said control part, and on exceeding of a determined traction force in the belt webbing, said metal band is pulled through said baffle and is thereby plastically deformed.
    Type: Grant
    Filed: May 12, 1998
    Date of Patent: August 10, 1999
    Assignee: TRW Occupant Restraint Systems GmbH
    Inventor: Thomas Ludwig
  • Patent number: 5928319
    Abstract: A combined binary/decimal adder unit reduces the operation delay ine processing binary coded decimal operands and permit an increased cycle rate of a processor unit in which the combined binary/decimal adder unit is utilized. Pre-sums are generated for each decimal digit position in parallel to the generation and distribution of the carries over the total of decimal digit positions of the adder unit. The pre-sums anticipate the carry-in of the decimal positions and the need to perform six corrections after the carry-out signal of the highest decimal digit position has been generated. The carry-out signal of each decimal digit position is used in combination with operation control signals to select the correct pre-sum of the digit position.
    Type: Grant
    Filed: November 13, 1997
    Date of Patent: July 27, 1999
    Assignee: International Business Machines Corporation
    Inventors: Wilhelm Haller, Ulrich Krauch, Thomas Ludwig, Holger Wetter
  • Patent number: 5744996
    Abstract: An integrated semiconductor circuit for reducing power consumption, employing CMOS technology in which a transistor pair can be operated stably at different supply voltages. At each supply voltage the transistors have an associated threshold voltage which can be set via the well and substrate bias voltages. The substrate of the transistor pair is connected to a substrate bias voltage generator circuit and the well is connected to a well bias voltage generator circuit. An input signal representing the level of the supply voltage sets the respective bias voltages corresponding to the level of the supply voltage. Thus, the threshold voltage of each transistor is adapted to the existing supply voltage, thereby ensuring stable operation of the transistor pair. A battery driven data processing system with the integrated semiconductor circuit can attain an approximate 100 fold extension of the operating time of the battery.
    Type: Grant
    Filed: July 17, 1995
    Date of Patent: April 28, 1998
    Assignee: International Business Machines Corporation
    Inventors: Gunther Kotzle, Volker Kreuter, Thomas Ludwig, Helmut Schettler
  • Patent number: 5306866
    Abstract: A module containing an electronic package provides a housing for cooling and protecting the electronic package. A top metal shell and a bottom metal shell form a common cavity in which the package is embedded without touching the inner walls of the cavity. A flexible thermally conductive foil is fixed to each of the shells. The foil is adjustable to the surface of the package and is isolated from electrically conductive parts of the package. A cooling liquid fills the gaps between the metal shells and the foils. Flexible isolated circuit means connect the package to the outside of the housing, balancing means balance pressure and volume between the shells, and further means firmly hold together the housing.
    Type: Grant
    Filed: April 13, 1992
    Date of Patent: April 26, 1994
    Assignee: International Business Machines Corporation
    Inventors: Harald W. Gruber, Heinz G. Horbach, Gunther W. Kotzle, Thomas Ludwig, Helmut Schettler
  • Patent number: 5162264
    Abstract: Integrated circuit package comprising a power supply distribution wiring and a chip interconnection signal wiring both formed on the top surface of a passive semiconductor interconnection carrier (2) in which a power supply decoupling capacitor is implemented.Spaced wells (4) of a first conductivity type are provided in the surface of said carrier of a second conductivity type.The power supply distribution wiring comprises first and second conductive lines (5,6) within a first wiring level (WL1).Said first conductive lines (5) are deposited on the surface areas of said wells (4) in an ohmic contact relationship and said second conductive lines (6) are deposited on the surface areas of said carrier (2) between said wells (4) in an ohmic contact relationship.Said first and second conductive lines are connected to first and second terminals of the power supply, respectively, so that the junction capacitance between said wells (4) and the carrier material (2) embedding said wells forms said decoupling capacitor.
    Type: Grant
    Filed: May 7, 1991
    Date of Patent: November 10, 1992
    Assignee: International Business Machines Corporation
    Inventors: Werner O. Haug, Erich Klink, Karl E. Kroll, Thomas Ludwig, Helmut Schettler, Rainer Stahl, Otto M. Wagner
  • Patent number: 5016087
    Abstract: Integrated circuit package comprising a power supply distribution wiring and a chip interconnection signal wiring both formed on the top surface of a passive semiconductor interconnection carrier (2) in which a power supply decoupling capacitor is implemented.Spaced wells (4) of a first conductivity type are provided in the surface of said carrier of a second conductivity type.The power supply distribution wiring comprises first and second conductive lines (5,6) within a first wiring level (WL1).Said first conductive lines (5) are deposited on the surface areas of said wells (4) in an ohmic contact relationship and said second conductive lines (6) are deposited on the surface areas of said carrier (2) between said wells (4) in an ohmic contact relationship.Said first and second conductive lines are connected to first second terminals of the power supply, respectively, so that the junction capacitance between said wells (4) and the carrier material (2) embedding said wells forms said decoupling capacitor.
    Type: Grant
    Filed: February 15, 1990
    Date of Patent: May 14, 1991
    Assignee: International Business Machines Corporation
    Inventors: Werner O. Haug, Erich Klink, Karl E. Kroll, Thomas Ludwig, Helmut Schettler, Rainer Stahl, Otto M. Wagner
  • Patent number: 4967104
    Abstract: The present invention teaches an arrangement for increasing the output impedance of a power amplifier coupled to a capacitively loaded line during the switching of power levels by the amplifier on the line. The arrangement of the invention reduces undesired noise voltage during switching. The present invention achieves this end by using a control circuit composed of a differential amplifier which has one input fed from the junction of an impedance resistor and a transistor that simulate the power stage transistor in the power amplifier being switched. This control circuit provides control voltage outputs to power control transistors which are connected to and control the speed of the power stage transistors used to change and discharge the capcitively loaded line.
    Type: Grant
    Filed: October 2, 1989
    Date of Patent: October 30, 1990
    Assignee: International Business Machines Corporation
    Inventors: Thomas Ludwig, Helmut Schettler, Otto M. Wagner, Rainer Zuhlke
  • Patent number: 4815113
    Abstract: A method for the digital slope control of the output signals of power amplifiers, as well as a power amplifier suitable for carrying out the method as described. One way of representing the actual slope value is via the number of clock pulses applied to a counter during a measuring interval which depends in its duration on the slope. Such a measuring interval is produced by applying the pulses of a ring oscillator containing one of the power amplifiers to another counter until the overflow of the latter. Another mode of representing the actual slope value consists in counting the number of pulses of the ring oscillator during a measuring interval of predetermined duration. Actual and nominal values of the slope are compared. The results of this comparison change the contents of a left/right-shift register.
    Type: Grant
    Filed: October 20, 1987
    Date of Patent: March 21, 1989
    Assignee: International Business Machines Corporation
    Inventors: Thomas Ludwig, Helmut Schettler, Otto Wagner, Rainer Zuhlke
  • Patent number: 3982582
    Abstract: A method and apparatus for casting of metals into a continuous casting mold wherein metal is cast out of a ladle into a tundish having at least one non-regulatable bottom discharge and into at least one mold by means of a pouring tube. After the start of the casting operation the casting jet emanating from the bottom discharge is controlled and, if desired, corrected to the desired casting jet formation and thereafter the pouring tube is brought into the casting position through the casting jet.
    Type: Grant
    Filed: December 2, 1974
    Date of Patent: September 28, 1976
    Assignee: Concast AG
    Inventors: Eberhard Knorr, Thomas Ludwig Grunwald, Arno Oswald