Patents by Inventor Thomas Luedeke
Thomas Luedeke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9781120Abstract: A system on chip comprises a responder unit comprising a set of responder elements and an access control unit associated with an authorization list and the responder unit. An entry of the authorization list defines a set of access requirements in relation to an address space identifying at least part of the responder unit. The access control unit is arranged to: receive a request for access to a target responder element among the responder elements of the responder unit, determine the corresponding set of access requirements for the received access request from the authorization list, and evaluate the request for access with respect to the determined set of access requirements and generate a first request evaluation result.Type: GrantFiled: July 18, 2013Date of Patent: October 3, 2017Assignee: NXP USA, Inc.Inventors: Michael Rohleder, Gary Hay, Thomas Luedeke, Stephan Mueller
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Patent number: 9733952Abstract: A microprocessor comprises at least one reset management module. The at least one reset management module is arranged to detect a reset event, determine if at least one reset condition has been met upon detection of the reset event, and cause at least a part of the microprocessor to remain in a reset state upon determining that the at least one reset condition has been met.Type: GrantFiled: February 27, 2012Date of Patent: August 15, 2017Assignee: NXP USA, Inc.Inventors: Thomas Luedeke, Markus Baumeister, Carl Culshaw
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Patent number: 9448811Abstract: A microprocessor device comprises at least one reset management module. The at least one reset management module is arranged to detect a reset event comprising a first reset level, determine if at least one reset condition has been met upon detection of the reset event comprising the first reset level, and cause a reset of a second reset level upon determining that the at least one reset condition has been met.Type: GrantFiled: November 23, 2011Date of Patent: September 20, 2016Assignees: Freescale Semiconductor, Inc., STMicroelectronics SRLInventors: Carl Culshaw, Thomas Luedeke, Nicolas Grossier
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Publication number: 20160156632Abstract: A system on chip comprises a responder unit comprising a set of responder elements and an access control unit 484 associated with an authorization list and the responder unit. An entry of the authorization list defines a set of access requirements in relation to an address space identifying at least part of the responder unit. The access control unit is arranged to: receive a request for access to a target responder element among the responder elements of the responder unit, determine the corresponding set of access requirements for the received access request from the authorization list, and evaluate the request for access with respect to the determined set of access requirements and generate a first request evaluation result.Type: ApplicationFiled: July 18, 2013Publication date: June 2, 2016Applicant: Freescale Semiconductor, Inc.Inventors: Michael ROHLEDER, Gary HAY, Thomas LUEDEKE, Stephan MUELLER
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Patent number: 9024663Abstract: In a first circuit for detecting clock glitches in a clock signal, a master counter is clocked by the clock signal and memorizes a master count. An incrementer advances the master count by one increment. A slave counter is clocked by the clock signal and memorizes a slave count. The slave count is retarded relative to the master count by at least a particular number of clock edges. A comparator determines whether the difference between the master count and the slave count is at least a value of the incrementer times the particular number of clock edges.Type: GrantFiled: August 30, 2013Date of Patent: May 5, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Michael Rohleder, Thomas Koch, Vladimir Litovtchenko, Thomas Luedeke
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Publication number: 20140317395Abstract: A microprocessor comprises at least one reset management module. The at least one reset management module is arranged to detect a reset event, determine if at least one reset condition has been met upon detection of the reset event, and cause at least a part of the microprocessor to remain in a reset state upon determining that the at least one reset condition has been met.Type: ApplicationFiled: February 27, 2012Publication date: October 23, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Thomas Luedeke, Markus Baumeister, Carl Culshaw
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Publication number: 20140298005Abstract: A microprocessor device comprises at least one reset management module. The at least one reset management module is arranged to detect a reset event comprising a first reset level, determine if at least one reset condition has been met upon detection of the reset event comprising the first reset level, and cause a reset of a second reset level upon determining that the at least one reset condition has been met.Type: ApplicationFiled: November 23, 2011Publication date: October 2, 2014Applicants: ST MICROELECTRONICS S.R.L., FREESCALE SEMICONDUCTOR, INC.Inventors: Carl Culshaw, Thomas Luedeke, Nicolas Grossier
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Patent number: 8841946Abstract: An electronic circuit comprises a reset input for receiving an input reset signal, a clock input for receiving a clock signal, and a reset output for providing an output reset signal. And it comprises a synchronous reset signal path comprising a synchronization unit, arranged to receive the input reset signal and provide the input reset signal synchronized with the clock signal to the reset output when the clock signal is available, and an asynchronous reset signal path arranged to provide the input reset signal to the reset output when a current clock availability information in a clock monitoring signal indicates that the clock signal is not available.Type: GrantFiled: July 20, 2010Date of Patent: September 23, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Thomas Luedeke, Joachim Kruecken
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Publication number: 20140006841Abstract: In a first circuit for detecting clock glitches in a clock signal, a master counter is clocked by the clock signal and memorizes a master count. An incrementer advances the master count by one increment. A slave counter is clocked by the clock signal and memorizes a slave count. The slave count is retarded relative to the master count by at least a particular number of clock edges. A comparator determines whether the difference between the master count and the slave count is at least a value of the incrementer times the particular number of clock edges.Type: ApplicationFiled: August 30, 2013Publication date: January 2, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Michael Rohleder, Thomas Koch, Vladimir Litovtchenko, Thomas Luedeke
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Patent number: 8552764Abstract: In a first circuit for detecting clock glitches in a clock signal, a master counter is clocked by the clock signal and memorizes a master count. An incrementer advances the master count by one increment. A slave counter is clocked by the clock signal and memorizes a slave count. The slave count is retarded relative to the master count by at least a particular number of clock edges. A comparator determines whether the difference between the master count and the slave count is at least a value of the incrementer times the particular number of clock edges.Type: GrantFiled: January 5, 2009Date of Patent: October 8, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Michael Rohleder, Thomas Koch, Vladimir Litovtchenko, Thomas Luedeke
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Publication number: 20130181696Abstract: A low-voltage exit detector comprises a low-voltage detector and a voltage rise detector for detecting a change from a low-voltage condition of a watched voltage to a non-low-voltage condition of the watched voltage. An error detector for detecting storage errors comprises: a low-voltage exit detector as described above, first and second loaders for loading an load-ing information into first and second storage elements, wherein the loading information is coded using first and second coding schemes; first and second retrievers for retrieving stored information stored in the first and the second storage elements and decoding this information; and a second comparator for comparing a combination of a first retrieved information retrieved using the first retriever and a second retrieved information retrieved using the second retriever to each pattern of a set of valid patterns and for generating a match-mismatch signal indicating a result of this comparison.Type: ApplicationFiled: October 4, 2010Publication date: July 18, 2013Applicant: Freescale Semiconductor ,Inc.Inventors: Michael Rohleder, Stefan Doll, Thomas Luedeke
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Publication number: 20130113531Abstract: An electronic circuit comprises a reset input for receiving an input reset signal, a clock input for receiving a clock signal, and a reset output for providing an output reset signal. And it comprises a synchronous reset signal path comprising a synchronization unit, arranged to receive the input reset signal and provide the input reset signal synchronized with the clock signal to the reset output when the clock signal is available, and an asynchronous reset signal path arranged to provide the input reset signal to the reset output when a current clock availability information in a clock monitoring signal indicates that the clock signal is not available.Type: ApplicationFiled: July 20, 2010Publication date: May 9, 2013Applicant: Freescale Semiconductor, Inc.Inventors: Thomas Luedeke, Joachim Kruecken
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Patent number: 8214722Abstract: A signal error determination and correction system is provided which comprises an error correction value calculation means which processes a predetermined segment of a signal to calculate an error correction value, and a signal correction means and prediction which applies the error correction value to at least part of the signal to correct the part of the signal. The invention further provides a method of signal error determination and correction.Type: GrantFiled: June 20, 2006Date of Patent: July 3, 2012Assignee: Freescale Semiconductor, Inc.Inventor: Thomas Luedeke
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Publication number: 20110317802Abstract: In a first circuit for detecting clock glitches in a clock signal, a master counter is clocked by the clock signal and memorizes a master count. An incrementer advances the master count by one increment. A slave counter is clocked by the clock signal and memorizes a slave count. The slave count is retarded relative to the master count by at least clock edges. A comparator determines whether the difference between the master count and the slave count is at least. In a related aspect, a synchronous circuit comprises a clock tree for transmitting a clock signal from a start point to one or more other points, the start point and the other points comprising a first point and second point. A first counter is clocked by the clock signal at the first point and memorizes a first count. A first incrementer advances the first count by one increment. A second counter is clocked by the clock signal at the second point and memorizes a second count. A second incrementer advances the second count by one increment.Type: ApplicationFiled: January 5, 2009Publication date: December 29, 2011Inventors: Michael Rohleder, Thomas Koch, Vladimir Litovtchenko, Thomas Luedeke
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Patent number: 7958281Abstract: A method of transmitting data to a recipient comprising the steps of dividing the data into a plurality of groups, providing a synchronizing means for each of the groups, using the synchronizing means to synchronize the data in each group, and transmitting the data to a recipient characterized in that the data is divided in accordance with its synchronization requirements with the recipient.Type: GrantFiled: June 20, 2006Date of Patent: June 7, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Thomas Luedeke, Christian Steffen
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Publication number: 20090193317Abstract: A signal error determination and correction system is provided which comprises an error correction value calculation means which processes a predetermined segment of a signal to calculate an error correction value, and a signal correction means and prediction which applies the error correction value to at least part of the signal to correct the part of the signal. The invention further provides a method of signal error determination and correction.Type: ApplicationFiled: June 20, 2006Publication date: July 30, 2009Applicant: Freescale Semiconductor, Inc.Inventor: Thomas Luedeke
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Publication number: 20090172216Abstract: A method of transmitting data to a recipient comprising the steps of dividing the data into a plurality of groups, providing a synchronising means for each of the groups, using the synchronising means to synchronise the data in each group, and transmitting the data to a recipient characterised in that the data is divided in accordance with its synchronisation requirements with the recipient.Type: ApplicationFiled: June 20, 2006Publication date: July 2, 2009Applicant: Freescale Semiconductor. Inc.Inventors: Thomas Luedeke, Christian Steffen