Abstract: Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.

Abstract: A metal etch processing sequence eliminates the need to use an organic masking layer solvent and etches a portion of an insulating layer after a plasma metal etching step. The etch of the insulating layer is performed with an etching solution that may include 1,2-ethanediol, hydrogen fluoride, and ammonium fluoride. The etching solution etches in a range of 100-900 angstroms of the insulating layer. The etch removes at least 75 percent of the mobile ions within the insulating layer, and should remove at least 95 percent of the mobile ions. The process may be implemented using an acid hood, an acid compatible spray tool, or a puddle processing tool. The process includes many different embodiments that allow the process to be easily integrated into many different existing processing sequences. A similar process may be used with a resist-etch-back processing sequence.