Abstract: A data encryption device with a plurality of data encryption boards for encrypting data is provided. In a preferred embodiment, the data encryption device has a monitor processor connected to a parallel bus. Each data encryption board has a parallel port for connection to the parallel bus and a serial port for connection to a host computer. Each data encryption board operates independently of the other data encryption boards. A plurality of data encryption boards may be connected to the bus. In operation, a host computer sends data to a data encryption board. The data encryption board encrypts the data and sends the encrypted data to the host processor. The monitor processor and the data encryption boards are preferably in the same housing unit with a tamper detection mechanism.

Abstract: An improved fault tolerant processor arrangement is described. In accordance with this invention, redundant processors are coupled in parallel in a master/slave configuration wherein means are provided for disabling the respective outputs of the processors. The master processor includes means for generating a periodic pulse which is detected by the slave processor. As long as the periodic pulse is detected by the slave processor, the output of the master processor remains enabled and the output of the slave processor is disabled. If the periodic pulse is not detected by the slave processor, the slave processor disables the output of the master processor wherein the output of the slave processor becomes enabled.