Abstract: A system, method and computer program product for supporting system initiated checkpoints in high performance parallel computing systems and storing of checkpoint data to a non-volatile memory storage device. The system and method generates selective control signals to perform checkpointing of system related data in presence of messaging activity associated with a user application running at the node. The checkpointing is initiated by the system such that checkpoint data of a plurality of network nodes may be obtained even in the presence of user applications running on highly parallel computers that include ongoing user messaging activity. In one embodiment, the non-volatile memory is a pluggable flash memory card.

Abstract: A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node individually or simultaneously work on any combination of computation or communication as required by the particular algorithm being solved. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency.

Abstract: A tall mezzanine connector which connects the substantial middle half of each of a pair of circuit cards positioned normal thereto in such a way that there is compliance when the two halves of the circuit cards are not in alignment. The mezzanine connector comprises a header and a receptacle that includes wafers having electrical contact means at each end thereof for contacting contacts in the respective circuit cards, the wafers being held in place by an upper base member and a lower base member.

Abstract: A tall mezzanine connector which connects the substantial middle half of each of a pair of circuit cards positioned normal thereto. The mezzanine connector comprises a and a receptacle that includes wafers having electrical contact means at each end thereof for contacting contacts in the respective circuit cards, the wafers being held in place by an upper base member and a lower base member.

Abstract: A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node individually or simultaneously work on any combination of computation or communication as required by the particular algorithm being solved. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency.

Abstract: A tall mezzanine connector which connects the substantial middle half of each of a pair of circuit cards positioned normal thereto. The mezzanine connector comprises a and a receptacle that includes wafers having electrical contact means at each end thereof for contacting contacts in the respective circuit cards, the wafers being held in place by an upper base member and a lower base member.

Abstract: A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System- On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node individually or simultaneously work on any combination of computation or communication as required by the particular algorithm being solved. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency.

Abstract: A tall mezzanine connector which connects the substantial middle half of each of a pair of circuit cards positioned normal thereto in such a way that there is compliance when the two halves of the circuit cards are not in alignment. The mezzanine connector comprises a header and a receptacle that includes wafers having electrical contact means at each end thereof for contacting contacts in the respective circuit cards, the wafers being held in place by an upper base member and a lower base member.

Abstract: A cooling apparatus, system and like method for an electronic device includes a plurality of heat producing electronic devices affixed to a wiring substrate. A plurality of heat transfer assemblies each include heat spreaders and thermally communicate with the heat producing electronic devices for transferring heat from the heat producing electronic devices to the heat transfer assemblies. The plurality of heat producing electronic devices and respective heat transfer assemblies are positioned on the wiring substrate having the regions overlapping. A heat conduit thermally communicates with the heat transfer assemblies. The heat conduit circulates thermally conductive fluid therethrough in a closed loop for transferring heat to the fluid from the heat transfer assemblies via the heat spreader.

Abstract: A cooling or heat transfer apparatus and method is disclosed for cooling an electronic device. The apparatus includes a heat producing electronic device which may include an electronic circuit card with many heat sources. A heat transfer device is connected to the heat producing electronic device which is thermally communicating with the heat producing device for transferring heat from the heat producing device to the heat transfer device. A heat conduit is connected to the heat transfer device and thermally communicating with the heat transfer device for transferring heat to the heat conduit from the heat transfer device. A cooling housing is connected to the heat conduit and the cooling housing thermally communicating with the heat conduit for transferring heat to the cooling housing from the heat conduit. The apparatus enables the replacement of circuit cards in the field because it eliminates the need to apply thermal-interface materials.

Abstract: A system, method and computer program product for supporting system initiated checkpoints in high performance parallel computing systems and storing of checkpoint data to a non-volatile memory storage device. The system and method generates selective control signals to perform checkpointing of system related data in presence of messaging activity associated with a user application running at the node. The checkpointing is initiated by the system such that checkpoint data of a plurality of network nodes may be obtained even in the presence of user applications running on highly parallel computers that include ongoing user messaging activity. In one embodiment, the non-volatile memory is a pluggable flash memory card.

Abstract: A massively parallel supercomputer of petaOPS-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC) having up to four processing elements. The ASIC nodes are interconnected by multiple independent networks that optimally maximize the throughput of packet communications between nodes with minimal latency. The multiple networks may include three high-speed networks for parallel algorithm message passing including a Torus, collective network, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. The use of a DMA engine is provided to facilitate message passing among the nodes without the expenditure of processing resources at the node.

Abstract: A heatsink structure and method for the cooling of closely spaced packaged heat-producing devices, such as dual-in-line memory modules (DIMMs). A folded sheet metal heatsink structure is provided which is constituted of a coined metallic material and which has a large plurality of waffle-shaped ridges extending therefrom constituting additional surface areas which are adapted to enable heat generated by hub chips to pass upwardly and then outwardly through waffle-like ridges and, thus, dissipated to the exterior, thereby imparting an improved degree of cooling to heat-producing components or devices.

Abstract: A cooling apparatus, system and like method for an electronic device includes a plurality of heat producing electronic devices affixed to a wiring substrate. A plurality of heat transfer assemblies each include heat spreaders and thermally communicate with the heat producing electronic devices for transferring heat from the heat producing electronic devices to the heat transfer assemblies The plurality of heat producing electronic devices and respective heat transfer assemblies are positioned on the wiring substrate having the regions overlapping. A heat conduit thermally communicates with the heat transfer assemblies. The heat conduit circulates thermally conductive fluid therethrough in a closed loop for transferring heat to the fluid from the heat transfer assemblies via the heat spreader.

Abstract: A heatsink structure and method for the cooling of closely spaced packaged heat-producing devices, such as dual-in-line memory modules (DIMMs). A folded sheet metal heatsink structure is provided which is constituted of a coined metallic material and which has a large plurality of waffle-shaped ridges extending therefrom constituting additional surface areas which are adapted to enable heat generated by hub chips to pass upwardly and then outwardly through waffle-like ridges and, thus, dissipated to the exterior, thereby imparting an improved degree of cooling to heat-producing components or devices.

Abstract: A cooling or heat transfer apparatus and method is disclosed for cooling an electronic device. The apparatus includes a heat producing electronic device which may include an electronic circuit card with many heat sources. A heat transfer device is connected to the heat producing electronic device which is thermally communicating with the heat producing device for transferring heat from the heat producing device to the heat transfer device. A heat conduit is connected to the heat transfer device and thermally communicating with the heat transfer device for transferring heat to the heat conduit from the heat transfer device. A cooling housing is connected to the heat conduit and the cooling housing thermally communicating with the heat conduit for transferring heat to the cooling housing from the heat conduit. The apparatus enables the replacement of circuit cards in the field because it eliminates the need to apply thermal-interface materials.

Abstract: A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node may be used individually or simultaneously to work on any combination of computation or communication as required by the particular algorithm being solved or executed at any point in time. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency.

Abstract: A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node may be used individually or simultaneously to work on any combination of computation or communication as required by the particular algorithm being solved or executed at any point in time. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency.

Abstract: A fansink arrangement for a laptop computer wherein two distinct patterns of air intake can be employed. Particularly, dual air intakes of the laptop can be managed and controlled depending upon an operating mode of the computer. Thus, when the computer is in a “stand alone” mode, only one air intake is employed while in a “docking” mode of the computer two air intakes are employed.

Abstract: A novel massively parallel supercomputer of petaOPS-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC) having up to four processing elements. The ASIC nodes are interconnected by multiple independent networks that optimally maximize the throughput of packet communications between nodes with minimal latency. The multiple networks may include three high-speed networks for parallel algorithm message passing including a Torus, collective network, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. Novel use of a DMA engine is provided to facilitate message passing among the nodes without the expenditure of processing resources at the node.