Abstract: The present disclosure provides a respiratory protection device that includes a valve assembly operable between an open configuration and a closed configuration. In some exemplary embodiments, the respiratory protection device includes an elastomeric seal, and a valve assembly and a breathing air source component are in sealing engagement with the elastomeric seal when the valve assembly is in the closed configuration.

Abstract: A buffered memory module including a downstream buffer, a downstream receiver, an upstream driver, an upstream receiver. The downstream buffer and the downstream receiver are both adapted for connection to a downstream memory bus in a packetized cascaded interconnect memory subsystem. The upstream driver and the upstream receiver are both adapted for connection to an upstream memory bus in the memory subsystem. During a test of the memory module, the upstream driver is connected to the downstream receiver and the downstream driver is connected to the upstream receiver. The memory module also includes one or more storage registers, a microprocessor and a service interface port. The microprocessor includes instructions for executing the test of the memory module including storing results of the test in the storage registers. The service interface port receives service interface signals that initiate the execution of the test and accesses the storage registers to determine the results of the test.

Abstract: A buffer device for testing a memory subsystem. The buffer device includes a parallel bus port adapted for connection to a slow speed bus and a serial bus port adapted for connection to a high speed bus. The high speed bus operates at a faster speed than the slow speed bus. The buffer device also includes a bus converter having a standard operating mode for converting serial packetized input data received via the serial bus port into parallel bus output data for output via the parallel bus port. The buffer device also includes an alternate operating mode for converting parallel bus input data received via the parallel bus port into serial packetized output data for output via the serial bus port. The serial packetized input data is consistent in function and timing to the serial packetized output data.

Abstract: A buffer device for testing a memory subsystem. The buffer device includes a parallel bus port adapted for connection to a slow speed bus and a serial bus port adapted for connection to a high speed bus. The high speed bus operates at a faster speed than the slow speed bus. The buffer device also includes a bus converter having a standard operating mode for converting serial packetized input data received via the serial bus port into parallel bus output data for output via the parallel bus port. The buffer device also includes an alternate operating mode for converting parallel bus input data received via the parallel bus port into serial packetized output data for output via the serial bus port. The serial packetized input data is consistent in function and timing to the serial packetized output data.

Abstract: A buffered memory module including a downstream buffer, a downstream receiver, an upstream driver, an upstream receiver. The downstream buffer and the downstream receiver are both adapted for connection to a downstream memory bus in a packetized cascaded interconnect memory subsystem. The upstream driver and the upstream receiver are both adapted for connection to an upstream memory bus in the memory subsystem. During a test of the memory module, the upstream driver is connected to the downstream receiver and the downstream driver is connected to the upstream receiver. The memory module also includes one or more storage registers, a microprocessor and a service interface port. The microprocessor includes instructions for executing the test of the memory module including storing results of the test in the storage registers. The service interface port receives service interface signals that initiate the execution of the test and accesses the storage registers to determine the results of the test.

Abstract: A power supply control circuit for conditioning an electronic circuit's input voltage at ground or at the operation voltage of an external power supply so as to permit the electronic circuit to receive a supply voltage at ground potential until the power supply transitions above a threshold voltage level and thereafter to provide operation level voltage of the power supply to the electronic circuit. The circuit comprises a transconducting means having its high current node coupled to an external power supply, its controlling node coupled to a voltage reference means. The transconducting means has its controlled high current node coupled through a power input node to the power input for the electronic circuit to condition the voltage received thereby. The power input node is in turn coupled through a pull down means to ground potential.

Abstract: A method and apparatus for sequencing the operation of electronic circuits based upon the level of the voltage provided by an external power supply. One or more power supply sequencer circuits may be interposed between an external power supply and one or more electronic circuits. The power supply sequencer circuits comprise a transistor having its high current node coupled to an external power supply, its controlling node coupled to a voltage sequencing means such as a diode and a resistor, wherein the resistor is in turn coupled to the external power supply and the diode is coupled to the ground potential. The transistor has its controlled high current node coupled through a power input node to the power input for the electronic circuit to condition the voltage received thereby. The power input node is in turn coupled through a second resistor to ground potential.