Patents by Inventor Thomas M. Henige
Thomas M. Henige has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9634693Abstract: An apparatus and method decode LDPC code. The apparatus includes a memory and a number of LDPC processing elements. The memory is configured to receive a LDPC codeword having a length equal to a lifting factor times a base LDPC code length, wherein the lifting factor is greater than one. The number of LDPC processing elements configured to decode the LDPC codeword, wherein each of the number of LDPC processing elements decode separate portions of the LDPC codeword.Type: GrantFiled: September 29, 2011Date of Patent: April 25, 2017Assignee: SAMSUNG ELECTRONICS CO., LTDInventors: Eran Pisek, Shadi Abu-Surra, Thomas M. Henige
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Patent number: 9264073Abstract: A low-density parity check (LDPC) decoder includes a memory configured to store multiple variable node LLR values in a LLR memory and multiple check nodes messages in a CN memory. The LDPC decoder also includes a saturation indicator configured to determine whether each check node of the H-matrix becomes saturated, and a multiplexer. The multiplexer is configured store an extrinsic check node value in the CN memory and updated LLR value in the LLR memory when the variable node is not saturated; and store a freeze input value in the CN memory and a freeze value in the LLR memory when the variable node is saturated.Type: GrantFiled: August 27, 2012Date of Patent: February 16, 2016Assignee: Samsung Electronics Co., LtdInventors: Mehrzad Malmirchegini, Shadi Abu-surra, Thomas M. Henige, Eran Pisek
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Patent number: 8627166Abstract: A method constructs a family of low-density-parity-check (LDPC) codes. The method includes identifying a code rate for an LDPC code in the family, identifying a protograph for the LDPC code, and constructing a base matrix for the LDPC code. The base matrix is constructed by replacing each zero in the protograph with a ‘?1’, selecting a corresponding value for an absolute shift for each one in the protograph based on constraining a number of relative shifts per column of the LDPC code to one and increasing a size of a smallest cycle in a graph of the LDPC code, and replacing each one in the protograph with the corresponding value.Type: GrantFiled: November 29, 2011Date of Patent: January 7, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Shadi Abu-Surra, Thomas M. Henige, Eran Pisek, Zhouyue Pi
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Patent number: 8606259Abstract: A method for testing a software-defined radio (SDR) device is provided. The method includes configuring the SDR device for a first standard. A first test is performed on the SDR device under the first standard. Test data for the first test is received from the SDR device. A switching time for configuring the SDR device for the first standard is determined based on the test data for the first test.Type: GrantFiled: January 19, 2007Date of Patent: December 10, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Thirumalarao Voonna, Jasmin Oz, Eran Pisek, Thomas M. Henige
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Patent number: 8417756Abstract: A method of a hardware based Montgomery reduction contemplates preparing a table comprising a plurality of sets of values of 2K+i (mod n), 2K+i+1 (mod n) and (2K+i+2K+i+1)(mod n), where i=0 to M?2, n is a modulo number, K is an integer, and M is a number of significant bits in a binary Y; selecting one of the values within one of the plurality of sets of the table in dependence upon a value of two neighboring bits Yi+1,i of the binary Y; adding two neighboring selected values and calculating the modulo value of the sum value with the modulo number n; repeatedly adding two neighboring calculated modulo values and calculating the modulo value of the intermediate sum of the two neighboring calculated modulo values until only a single calculated module value is obtained; and setting the single value as the Montgomery representation.Type: GrantFiled: July 11, 2008Date of Patent: April 9, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Eran Pisek, Thomas M. Henige
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Publication number: 20130061114Abstract: A low-density parity check (LDPC) decoder includes a memory configured to store multiple variable node LLR values in a LLR memory and multiple check nodes messages in a CN memory. The LDPC decoder also includes a saturation indicator configured to determine whether each check node of the H-matrix becomes saturated, and a multiplexer. The multiplexer is configured store an extrinsic check node value in the CN memory and updated LLR value in the LLR memory when the variable node is not saturated; and store a freeze input value in the CN memory and a freeze value in the LLR memory when the variable node is saturated.Type: ApplicationFiled: August 27, 2012Publication date: March 7, 2013Applicant: Samsung Electronics Co., Ltd.Inventors: Mehrzad Malmirchegini, Shadi Abu-Surra, Thomas M. Henige, Eran Pisek
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Publication number: 20120240001Abstract: A method constructs a family of low-density-parity-check (LDPC) codes. The method includes identifying a code rate for an LDPC code in the family, identifying a protograph for the LDPC code, and constructing a base matrix for the LDPC code. The base matrix is constructed by replacing each zero in the protograph with a ‘?1’, selecting a corresponding value for an absolute shift for each one in the protograph based on constraining a number of relative shifts per column of the LDPC code to one and increasing a size of a smallest cycle in a graph of the LDPC code, and replacing each one in the protograph with the corresponding value.Type: ApplicationFiled: November 29, 2011Publication date: September 20, 2012Applicant: Samsung Electronics Co., Ltd.Inventors: Shadi Abu-Surra, Thomas M. Henige, Eran Pisek, Zhouyue Pi
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Patent number: 8218518Abstract: A software-defined radio (SDR) system that operates under a plurality of wireless communication standards. The SDR system comprises a reconfigurable maximum aposteriori probability (MAP) decoder capable of being configured under software control to decode a received data block according to a select wireless communication standard and a reconfigurable interleaver associated with the reconfigurable MAP decoder. The reconfigurable interleaver comprises a reconfigurable interleaver core circuitry capable of being configured under software control to operate according to the selected wireless communication standard and a unified interleaver interface for coupling a defined set of control and bus signals from the reconfigurable MAP decoder to the reconfigurable interleaver core circuitry.Type: GrantFiled: May 18, 2007Date of Patent: July 10, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Eran Pisek, Thomas M. Henige
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Publication number: 20120084625Abstract: An apparatus and method decode LDPC code. The apparatus includes a memory and a number of LDPC processing elements. The memory is configured to receive a LDPC codeword having a length equal to a lifting factor times a base LDPC code length, wherein the lifting factor is greater than one. The number of LDPC processing elements configured to decode the LDPC codeword, wherein each of the number of LDPC processing elements decode separate portions of the LDPC codeword.Type: ApplicationFiled: September 29, 2011Publication date: April 5, 2012Applicant: Samsung Electronics Co., Ltd.Inventors: Eran Pisek, Shadi Abu-Surra, Thomas M. Henige
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Patent number: 8032811Abstract: An almost regular permutation (ARP) interleaver and method generate interleaved indices in a sequential fashion based on a process in which each interleaved index is a function of an adjacent index. Based on the data block size (N) for a received data block and a constant (C) for the ARP interleaver, a plurality of interleaved indices is generated. For one embodiment in which the interleaved indices are generated in forward sequence, the adjacent interleaved index is the immediately previous index, P(j?1), and each interleaved index (P(j)) is generated based on incrementing the previous interleaved index (P(j?1)) by an incremental value k(i), where j represents a non-interleaved index between 0 and N?1, i represents a modulo-C counter index that corresponds to j, k(i) represents the i-th value of a set of incremental values associated with N and C.Type: GrantFiled: March 7, 2007Date of Patent: October 4, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Thomas M. Henige, Eran Pisek
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Patent number: 7895497Abstract: A maximum a posteriori probability (MAP) block decoder for decoding a received data block of input samples. The MAP block decoder segments the received data block into at least a first segment and a second segment and calculates and stores alpha values during forward processing of the first segment. The MAP block decoder uses a first selected alpha value calculated during forward processing of the first segment as initial state information during forward processing of the second segment. The first and second segments may overlap each other, such that the last M samples of the first segment are the same as the first M samples of the second segment.Type: GrantFiled: November 29, 2006Date of Patent: February 22, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Eran Pisek, Thomas M. Henige
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Publication number: 20090144353Abstract: A method of a hardware based Montgomery reduction contemplates preparing a table comprising a plurality of sets of values of 2K+i (mod n), 2K+i+1 (mod n) and (2K+i+2K+i+1)(mod n), where i=to M?2, n is a modulo number, K is an integer, and M is a number of significant bits in a binary Y; selecting one of the values within one of the plurality of sets of the table in dependence upon a value of two neighboring bits Yi+1,i of the binary Y; adding two neighboring selected values and calculating the modulo value of the sum value with the modulo number n; repeatedly adding two neighboring calculated modulo values and calculating the modulo value of the intermediate sum of the two neighboring calculated modulo values until only a single calculated module value is obtained; and setting the single value as the Montgomery representation.Type: ApplicationFiled: July 11, 2008Publication date: June 4, 2009Inventors: Eran Pisek, Thomas M. Henige
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Publication number: 20080123781Abstract: A maximum a posteriori probability (MAP) block decoder for decoding a received data block of input samples. The MAP block decoder segments the received data block into at least a first segment and a second segment and calculates and stores alpha values during forward processing of the first segment. The MAP block decoder uses a first selected alpha value calculated during forward processing of the first segment as initial state information during forward processing of the second segment. The first and second segments may overlap each other, such that the last M samples of the first segment are the same as the first M samples of the second segment.Type: ApplicationFiled: November 29, 2006Publication date: May 29, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eran Pisek, Thomas M. Henige
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Publication number: 20080115032Abstract: A method for operating an ARP interleaver is provided that includes generating each of a plurality of interleaved indices, P(j), as a function of an adjacent interleaved index. For one embodiment, the adjacent interleaved index is the immediately previous index, P(j?1), and each of the interleaved indices, P(j), is generated based on the following formula: P(j)=[P(j?1)+P0+d(j)?d(j?1)]mod N, where N comprises a data block size, P0 comprises a constant that is dependent on N, and d(j) comprises a dither vector.Type: ApplicationFiled: March 7, 2007Publication date: May 15, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Thomas M. Henige, Eran Pisek
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Publication number: 20080003949Abstract: A method for testing a software-defined radio (SDR) device is provided. The method includes configuring the SDR device for a first standard. A first test is performed on the SDR device under the first standard. Test data for the first test is received from the SDR device. A switching time for configuring the SDR device for the first standard is determined based on the test data for the first test.Type: ApplicationFiled: January 19, 2007Publication date: January 3, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Thirumalarao Voonna, Jasmin Oz, Eran Pisek, Thomas M. Henige