Abstract: A communication bus (14) provides bidirectional data communication between a computer (12) and various peripheral units including input/output processors (18, 20) and a service processor (22). The computer includes a memory control unit (24) which is connected to a memory array (26). A central processor unit (30) is connected for data exchange with the memory control unit (24). Data blocks are transferred through the bus (14) and either originate or terminate at the memory array (26). A peripheral unit, such as the processor (18) transfers a data block by first transferring a header parcel (146) which defines an address, block length and type of function. This is transmitted to the memory control unit (24) which carries out the desired data transfer by sending or receiving sequential data parcels. An interrupt bus (16) connects each of the units of the computer system (10) including the processors (18, 20, 22) and the central processing unit (30).

Abstract: An operand processing unit (10) carries out processing of operands in a computer. The unit (10) includes a plurality of operation circuits (12, 14, 16, 18, 20). A source bus (22) provides one operand per clock cycle to the operation circuits (12, 14, 16, 18, 20). A destination bus (24) receives one resultant per clock cycle from the operation circuits (12, 14, 16, 18, 20). Within each operation circuit there is provided an operand processing circuit (80) which performs a selected function with the received operands. These functions include, for example, multiplication, division, addition, subtraction, logical AND, and shift. Logical circuitry provides a priority assignment to the operation circuits (12, 14, 16, 18, 20) for sequencing the loading of operands into the highest priority operation circuit (12, 14, 16, 18, 20) which is not busy processing operands within its corresponding operand processing circuit (80).

Abstract: A diagnostic circuit is used to test the operation of a complex digital system by transferring operands to and from a plurality of registers (12, 14, 16). In a typical application the registers (12, 14, 16) in operation utilize parallel data transfers. For diagnostic purposes the registers (12, 14, 16) are connected serially and, in response to selected shift commands, data can be shifted either right or left through the registers (12, 14, 16). First and second buses (18, 20) provide serial, bidirectional paths for data transfer between the group of registers (12, 14, 16) and a service processing unit (26). In response to commands generated by the service processing unit (26) the registers (12, 14, 16) can be loaded right or left and read right or left. Whenever data is being read from the registers (12, 14, 16) the output data is recirculated back into the registers such that a complete cycle results in the original state being restored in the registers (12, 14, 16).

Abstract: Encachement apparatus consisting of first and second caches responsive to first and second keys, respectively, for outputting first and second data therefrom. In one embodiment, the second cache which includes a stack having a plurality of frames, outputs data contained in a current frame thereof in response to a second key which is obtained from the first cache. The data outputted from each cache is received substantially simultaneously at a combiner which combines such data to produce the desired third data from the dual cache system.

Abstract: A digital computer system having a memory system organized into objects for storing items of information and a processor for processing data in response to instructions. An object identifier code is associated with each object. The objects include procedure objects and data objects. The procedure objects contain procedures including the instructions and name tables associated with the procedures. The instructions contain operation codes and names representing data. Each name corresponds to a name table entry in the name table associated with the procedure. The name table for a name contains information from which the processor may determine the location and the format for the data (e.g., an operand) represented by the name.

Abstract: A vector processing computer is configured to operate in a pipelined fashion wherein each of the functional units is essentially independent and is designed to carry out its operational function in the fastest possible manner. Vector elements are transmitted from memory, either main memory, a physical cache unit or a logical cache through a source bus where the elements are alternately loaded into the vector processing units. The vector control unit decodes the vector instructions and generates the required control commands for operating the registers and logical units within the vector processing units. Thus, the vector processing units essentially work in parallel to double the processing rate. The resulting vectors are transmitted through a destination bus to either the physical cache unit, the main memory, the logical cache or to an input/output processor.

Abstract: The processor of the present invention can execute any of a plurality of dialects of "S-Language" instructions. S-Languages are of a higher order than typical machine languages but of a lower order than the user's own high order language. They can be tailored for compatibility with user high order languages. Each instruction of a particular S-Language is interpreted by a sequence of microinstructions. In the processor of the present invention, dispatching to the microinstruction sequencer is controlled jointly by the instruction bit pattern and the current contents of a dialect register. Each procedure to be executed carries with it information from which the appropriate contents of the dialect register may be determined. Thus, the processor of the present invention can always operate as an effective optimum processor for executing the procedure regardless of the source language chosen for writing that procedure.

Abstract: A continuous gas fluidized bed process is disclosed for the production of polymer from monomer wherein a gaseous stream comprising monomer is passed through a fluidized bed in a reaction zone in the presence of catalyst under reactive conditions, withdrawing from the reaction zone polymeric product and a stream comprising unreacted gases and solid particles, cooling the stream and recycling the cooled stream to the reaction zone together with sufficient additional monomer to replace monomer polymerized and withdrawn as polymer product, and wherein at least a part of the recycle stream is cooled to condense a portion thereof and form a liquid-containing mixture wherein the weight ratio of liquid to solid particles is not less than about two to one, and introducing the mixture into the reaction zone wherein the liquid in the mixture is vaporized.

Abstract: A process is described for increasing the space time yield of polymer production in a fluidized bed reactor employing an exothermic polymerization reaction by cooling the recycle stream to below its dew point and returning the resultant two-phase fluid stream to the reactor to maintain the fluidized bed at a desired temperature above the dew point of the recycle stream.

Abstract: A digital computer system in which data storage is referred to by a descriptor comprising an object number denoting a variable-length block of storage, an offset indicating how far into that block a desired data item begins, and a length field denoting the length of the desired data item. Separate means exist for manipulating each of the three descriptor portions, thus facilitating repetitive operations on related or contiguous operands. Various levels of microcode control are included. Each level of microcode control has its own stack, facilitating interrupts between levels. Stacks are duplicated in "secure stacks" in memory to protect against loss of state data from the stacks.

Abstract: A digital data system having a memory with a unique multi-ported memory I/O means. Separate means are provided for communicating with any of several buses. Address information, operands, instructions and Input/Output data may be separately sent and received over various of the buses.

Abstract: An improved process for the production of highly concentrated (N-P.sub.2 O.sub.5) suspension fertilizers effected by the ammoniation of wet-process or other impure orthophosphoric acids in batch-type equipment. The underlying concept which goes to the gist of the instant invention involves the use of a heel of product from a previously prepared batch to provide nuclei and a suitable environment for the conversion of the metallic impurities therein into crystalline habits rather than the usual highly undesirable form of metallic impurity gel-like compounds, which gels cause extremely high viscosities, nonpourability, and complete destruction of fluidity in concentrated ammonium phosphate suspension fertilizers prepared by prior-art procedure.

Abstract: A digital computer uses a memory which is structured into objects, which are blocks of storage of arbitrary length, in which data items are accessed by descriptors which for a desired data item specify the object, the offset into that object, and the length of the data object. The computer system of the present invention further provides the ability to execute any of a plurality of dialects of internal instructions, the repertoire of such dialects being virtually infinite, since there is the ability to load a supporting microcode during operation as needed.

Abstract: A digital data processing system has a memory organized into objects containing at least operands and instructions. Each object is identified by a unique and permanent identifier code which identifies the data processing system and the object. The system utilizes unique addressing mechanisms the addresses of which have object fields, offset fields and length fields for specifying the location and the total number of bits of an addressed object. The system uses a protection technique to prevent unauthorized access to objects by users who are identified by a subject number which identifies the user, a process of the system for executing the user's procedure, and the type of operation of the system to be performed by the user's procedure. An access control list for each object includes an access control list entry for each subject having access rights to the object and means for confirming that a particular active subject has access rights to a particular object before permitting access to the object.

Abstract: A digital data processing system has a memory organized into objects containing at least operands and instructions. Each object is identified by a unique and permanent identifier code which identifies the data processing system and the object. The system further uses multilevel microcode techniques for controlling sequences of microinstructions and for controlling the interval operations of the processor. The system uses a protection technique to prevent unauthorized access to objects by users who are identified by a subject number which identifies the user, a process of the system for executing a user's procedure, and the type of operation of the system to be performed by the user's procedure. An access control list for each object includes an access control list entry for each subject having access rights to the object and means for confirming that a particular active subject has access rights to a particular object before permitting access to the object.

Abstract: A data processing system having a flexible internal structure, protected from and effecitvely invisible to users, with multilevel control and stack mechanisms and capability of performing multiple, concurrent operations, and providing a flexible, simplified interface to users. The system is internally comprised of a plurality of separate, independent processors, each having a separate microinstruction control and at least one separate, independent port to a central communications and memory node. The communications and memory node is an independent processor having separate, independent microinstruction control and comprised of a plurality of independently operating, microinstruction controlled processors capable of performing multiple, concurrent memory and communications operations. Addressing mechanisms allow permanent, unique identification of information and an extremely large address space accessible and common to all such systems. Addresses are independent of system physical configuration.

Abstract: A data processing system having a flexible internal structure, protected from and effectively invisible to users, with multilevel control and stack mechanisms and capability of performing multiple, concurrent operations, and providing a flexible, simplified interface to users. The system is internally comprised of a plurality of separate, independent processors, each having a separate microinstruction control and at least one separate, independent port to a central communications and memory node. The communications and memory node is an independent processor having separate, independent microinstruction control and comprised of a plurality of independently operating, microinstruction controlled processors capable of performing multiple, concurrent memory and communications operations. Addressing mechanisms allow permanent, unique identification of information and an extremely large address space accessible and common to all such systems. Addresses are independent of system physical configuration.

Abstract: Hydroxylammonium salts are manufactured by a process comprising the catalytic reduction of nitric oxide with hydrogen in a dilute aqueous mineral acid in the presence of a suspended platinum catalyst at an elevated temperature, wherein the reaction is carried out in vessels of which the walls consist of conventional copper-containing austenitic chromium-nickel steels which contain from 16 to 28% by weight of chromium, from 32 to 50% by weight of nickel, from 1 to 4% by weight of molybdenum, up to 4% by weight of copper and at most 0.1% by weight of carbon and which in addition contain an amount of titanium which is at least 5 times the amount of carbon but is not more than 1% by weight, or an amount of niobium or tantalum which is at least 8 times the amount of carbon but is not more than 1.5% by weight.

Abstract: A system for performing operations on data items in digital computer systems in which the instructions may not specify internal registers in the processor as destinations of data received from memory or sources of data provided to memory. The system includes a result memory, apparatus for executing operations, instructions containing operation codes which specify that the result memory is to be a source of data to be operated on by the apparatus for executing operations, and control apparatus responsive to the operation codes for controlling the apparatus for executing operations. The result memory stores only the results of previous operations and may serve only as an input to the apparatus for executing instructions. The apparatus for executing operations may receive items to be operated on from either the computer system memory or the result memory.

Abstract: A data processing system having a flexible internal structure, protected from and effectively invisible to users, with multilevel control and stack mechanisms and capability of performing multiple, concurrent operations, and providing a flexible, simplified interface to users. The system is internally comprised of a plurality of separate, independent processors, each having a separate microinstruction control and at least one separate, independent port to a central communications and memory node. The communications and memory node is an independent processor having separate, independent microinstruction control and comprised of a plurality of independently operating, microinstruction controlled processors capable of performing multiple, concurrent memory and communications operations. Addressing mechanisms allow permanent, unique identification of information as objects and an extremely large address space accessible and common to all such systems.