Abstract: According to the teachings of the present invention, a data path interface (16) for receiving an incoming signal (14) and facilitating an interface to a digital signal processor (18) includes a synchronizer (62) for determining a signaling frame in a processed signal received from the digital signal processor (18). The data path interface (16) also includes an idle code detector (76) operable to detect an idle code in the incoming signal (14) by comparing the incoming signal (14) to at least one user-programmable idle code pattern. The data path interface (16) further including a least significant bit detector (78) operable to detect a loss of information in the incoming signal (14) by monitoring the status of the least significant bit of each channel to determine whether that bit is stuck at a particular value.

Abstract: An echo canceler (10) includes an idle code density detector (12) that measures an idle code density over a period of time. The idle code density detector (12) includes an idle code detector (30) that identifies idle codes and non-idle codes. An idle code integrator (32) increments an idle code count (36) by a first weight factor (38) for each idle code identified by the idle code detector (30). The idle code integrator (32) decrements the idle code count (36) by a second weight factor (40) for each non-idle code identified by the idle code detector (30). A threshold detector (34) continuously compares the idle code count (36) to a threshold value (42). When the idle code count (36) exceeds the threshold value (42), the threshold detector (34) generates a control signal (22) to disable an adaptive filter (14) and a processor (18) of the echo canceler (10).