Abstract: Mechanisms are provided for generating a physical layout of an integrated circuit design. A logic description of the integrated circuit design is received that comprises a first logic description of an irregular logic block of the integrated circuit design and a second logic description of a regular logic block of the integrated circuit design. A manual design of the regular logic block of the integrated circuit design is performed based on user input and an automated design of the irregular logic block of the integrated circuit design is performed without user input. The manual design of the regular logic block and the automated design of the irregular logic block are then integrated into the integrated circuit design to generate a hybrid integrated circuit design.

Abstract: Mechanisms are provided for generating a physical layout of an integrated circuit design. A logic description of the integrated circuit design is received that comprises a first logic description of an irregular logic block of the integrated circuit design and a second logic description of a regular logic block of the integrated circuit design. A manual design of the regular logic block of the integrated circuit design is performed based on user input and an automated design of the irregular logic block of the integrated circuit design is performed without user input. The manual design of the regular logic block and the automated design of the irregular logic block are then integrated into the integrated circuit design to generate a hybrid integrated circuit design.

Abstract: A method includes removing a code segment from a hardware description language design to create a modified hardware description language design. The code segment represents at least one time sensitive path in the hardware description language design. The method includes creating a delta list of differences between the modified hardware description language design and a physical hardware representation that is logically equivalent to the hardware description language design. The method includes extracting a portion of the physical hardware representation that corresponds to the time sensitive path based, at least in part, on the delta list. The method also includes creating a structured hardware description language design of the time sensitive path using the extracted portion of the physical hardware representation, wherein the structured hardware description language design comprises structural information of the extracted portion of the physical hardware representation.

Abstract: A method includes removing a code segment from a hardware description language design to create a modified hardware description language design. The code segment represents at least one time sensitive path in the hardware description language design. The method includes creating a delta list of differences between the modified hardware description language design and a physical hardware representation that is logically equivalent to the hardware description language design. The method includes extracting a portion of the physical hardware representation that corresponds to the time sensitive path based, at least in part, on the delta list. The method also includes creating a structured hardware description language design of the time sensitive path using the extracted portion of the physical hardware representation, wherein the structured hardware description language design comprises structural information of the extracted portion of the physical hardware representation.