Abstract: An interface controller coupled between the main memory system and the I/O system of a large data processing system which controller is able to receive memory access requests from a number of different peripheral devices. The memory interface controller is provided with a data array for holding a number of data words fetched from memory which data array in turn is addressed by the output of an address array. The address array is an associative memory that can associate a given main memory address, of data in the data array, with a data array address containing data stored in main memory at that main memory address so that actual main memory access need not be required.

Abstract: A controller for communication between the auxiliary processor and a cache mechanism in the system interface which communication is to be carried on independently of main memory accesses required to update the cache mechanism in an overlapped manner.

Abstract: A two-level controller for a system interface between an auxiliary processor and main memory modules of a multiprocessing system which respective processor and system have different clock rates, memory access times and memory addressing capabilities. The two-level controller is formed of a hierarchy of two control stores wherein the receipt of a command code by the first control store from the processor causes it to address the second control store. Each control store is provided with program counter means to receive its respective address and to increment that address until it receives a new address so as to asynchronously control simultaneous operation of a memory interface to said memory modules and a cache mechanism coupled to the processor.