Patents by Inventor Thomas M. Trent

Thomas M. Trent has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040061198
    Abstract: A semiconductor device system for coupling with external circuitry. The system includes a control signal on a carrier substrate. A semiconductor device is attached to the carrier substrate with an impedance matching device coupled to the control signal.
    Type: Application
    Filed: October 1, 2003
    Publication date: April 1, 2004
    Inventors: Stanley N. Protigal, Wen-Foo Chern, Ward D. Parkinson, Leland R. Nevill, Gary M. Johnson, Thomas M. Trent, Kevin G. Duesman
  • Publication number: 20030205779
    Abstract: A semiconductor device system for coupling with external circuitry. The system includes a control signal on a carrier substrate. A semiconductor device is attached to the carrier substrate with an impedance matching device coupled to the control signal.
    Type: Application
    Filed: June 4, 2003
    Publication date: November 6, 2003
    Inventors: Stanley N. Protigal, Wen-Foo Chern, Ward D. Parkinson, Leland R. Nevill, Gary M. Johnson, Thomas M. Trent, Kevin G. Duesman
  • Patent number: 6448628
    Abstract: An extensive network of N-channel transistor formed capacitor, with one node tie directly to VCC power bus and the other node directly VSS power bus, is implemented throughout all open space available on the whole silicon chip (memory as well as logic chip), particularly those directly underneath the metal power bus to achieve an on-chip power bus decoupling capacitor with capacitance in excess of 0.001 &mgr;F.
    Type: Grant
    Filed: January 27, 2000
    Date of Patent: September 10, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Wen-Foo Chern, Ward D. Parkinson, Thomas M. Trent, Kevin G. Duesman
  • Publication number: 20020008264
    Abstract: An extensive network of N-channel transistor formed capacitor, with one node tie directly to Vcc power bus and the other node directly Vss power bus, is implemented throughout all open space available on the whole silicon chip (memory as well as logic chip), particularly those directly underneath the metal power bus to achieve an on-chip power bus decoupling capacitor with capacitance in excess of 0.001 &mgr;F.
    Type: Application
    Filed: January 27, 2000
    Publication date: January 24, 2002
    Inventors: Wen-foo Chern, Ward D. Parkinson, Thomas M. Trent, Kevin G. Duesman
  • Publication number: 20010042899
    Abstract: A SIMM (single in-line memory module) board is provided with a plurality of integrated semiconductor memory or other integrated semiconductor circuit devices which include, as a part of each integrated circuit device, a current spike leveling capacitor. The capacitor is on the die side of circuitry connecting the device to the board. By connecting the on-chip capacitors of the integrated circuit devices in parallel, sufficient capacitance is provided to stabilize current to all of the integrated circuit devices.
    Type: Application
    Filed: February 2, 2001
    Publication date: November 22, 2001
    Inventors: Stanley N. Protigal, Wen-Foo Chern, Ward D. Parkinson, Leland R. Nevill, Gary M. Johnson, Thomas M. Trent, Kevin G. Duesman
  • Patent number: 6184568
    Abstract: A SIMM (single in-line memory module) board is provided with a plurality of integrated semiconductor memory or other integrated semiconductor circuit devices which include, as a part of each integrated circuit device, a current spike leveling capacitor. The capacitor is on the die side of circuitry connecting the device to the board. By connecting the on chip capacitors of the integrated circuit devices in parallel, sufficient capacitance is provided to stabilize current to all of the circuit devices.
    Type: Grant
    Filed: November 7, 1997
    Date of Patent: February 6, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Stanley N. Protigal, Wen-Foo Chern, Ward D. Parkinson, Leland R. Nevill, Gary M. Johnson, Thomas M. Trent, Kevin G. Duesman
  • Patent number: 6124625
    Abstract: An extensive network of N-channel transistor formed capacitor, with one node tie directly to V.sub.CC power bus and the other node directly V.sub.SS power bus, is implemented throughout all open space available on the whole silicon chip (memory as well as logic chip), particularly those directly underneath the metal power bus to achieve an on-chip power bus decoupling capacitor with capacitance in excess of 0.001 .mu.F.
    Type: Grant
    Filed: August 21, 1997
    Date of Patent: September 26, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Wen-Foo Chern, Ward D. Parkinson, Thomas M. Trent, Kevin G. Duesman
  • Patent number: 5687109
    Abstract: A SIMM (single in-line memory module) board is provided with a plurality of integrated semiconductor memory or other integrated semiconductor circuit devices which include, as a part of each integrated circuit device, a current spike leveling capacitor. The capacitor is on the die side of circuitry connecting the device to the board. By connecting the on-chip capacitors of the integrated circuit devices in parallel, sufficient capacitance is provided to stabilize current to all of the integrated circuit devices.
    Type: Grant
    Filed: June 27, 1996
    Date of Patent: November 11, 1997
    Assignee: Micron Technology, Inc.
    Inventors: Stanley N. Protigal, Wen-Foo Chern, Ward D. Parkinson, Leland R. Nevill, Gary M. Johnson, Thomas M. Trent, Kevin G. Duesman
  • Patent number: 5307309
    Abstract: A SIMM (single in-line memory module) board is provided with a plurality of semiconductor memory devices which include, as a part of each memory device, a current spike leveling capacitor. The capacitor is on the die side of circuitry connecting the memory device to the board. By connecting the on-chip capacitors of the memory devices in parallel, sufficient capacitance is provided to stabilize current to all of the memory devices.
    Type: Grant
    Filed: March 19, 1993
    Date of Patent: April 26, 1994
    Assignee: Micron Technology, Inc.
    Inventors: Stanley N. Protigal, Web-Foo Chern, Ward D. Parkinson, Leland R. Nevill, Gary M. Johnson, Thomas M. Trent, Kevin G. Duesman
  • Patent number: 5266821
    Abstract: An extensive network of N-channel transistor formed capacitor, with one node tie directly to V.sub.cc power bus and the other node directly V.sub.ss power bus, is implemented throughout all open space available on the whole silicon chip (memory as well as logic chip), particularly those directly underneath the metal power bus to achieve an on-chip power bus decoupling capacitor with capacitance in excess of 0.001 .mu.F.
    Type: Grant
    Filed: November 2, 1992
    Date of Patent: November 30, 1993
    Assignee: Micron Technology, Inc.
    Inventors: Wen-Foo Chern, Ward D. Parkinson, Thomas M. Trent, Kevin G. Duesman
  • Patent number: 5032892
    Abstract: An integrated cirucuit is provided with a depletion mode filter capacitor, which reduces voltage spiking, while at the same time avoiding latchup problems caused by the capacitor. The depletion mode capacitor has a barrier layer which is doped to an opposite conductivity type as the integrated circuit's substrate, achieved by doping to provide an opposite difference from four valence electrons as the substrate. The barrier is formed as a part of a CMOS process, in a manner which avoids additional process steps. The capacitor is formed with one node connected to ground or substrate, and the other node directly to a power bus. The capacitor is located on open space available on the whole siliocn chip (memory as well as logic chip), particularly directly underneath the metal power bus to achieve an on-chip power bus decoupling capacitor wth capacitance in excess of 0.001 .mu.F.
    Type: Grant
    Filed: December 20, 1989
    Date of Patent: July 16, 1991
    Assignee: Micron Technology, Inc.
    Inventors: Wen-Foo Chern, Ward M. Parkinson, Thomas M. Trent, Kevin G. Duesman, James E. O'Toole
  • Patent number: 4924442
    Abstract: A voltage sensing circuit is used to rapidly pull up a high potential node of a reference array to a value of a high potential source reduced by a threshold voltage (V.sub.CC -V.sub.T). During an enable cycle, the high potential node is precharged to a potential of V.sub.CC -V.sub.T, which turns on a transistor gated to the V.sub.CC potential. This pulls the high potential node as rapidly as possible to a high level in order to speed up the sensing process. A potential maintenance circuit provides sufficient current from the high potential source to maintain a desired potential at the high potential node.
    Type: Grant
    Filed: September 30, 1988
    Date of Patent: May 8, 1990
    Assignee: Micron Technology, Inc.
    Inventors: Zhitong Chen, Gary M. Johnson, Ward D. Parkinson, Wen-Foo Chern, Tyler A. Lowrey, Thomas M. Trent
  • Patent number: 4914631
    Abstract: A memory array (e.g., DRAM) is provided with a potential maintenance circuit which provides sufficient current to maintain a high potential node of the memory array at a predetermined potential. The potential maintenance circuit is gated ON after receipt of a clock signal and gated OFF at the predetermined potential. This permits the high voltage node to be maintained, while reducing current requirements. The invention is particularly useful when used in conjunction with a circuit which rapidly pulls up the high node to a value of V.sub.CC -V.sub.T (where VT is a threshold voltage of a transistor).
    Type: Grant
    Filed: September 30, 1988
    Date of Patent: April 3, 1990
    Assignee: Micron Technology, Inc.
    Inventors: Gary M. Johnson, Zhitong Chen, Wen-Foo Chern, Ward D. Parkinson, Tyler A. Lowrey, Thomas M. Trent
  • Patent number: 4897568
    Abstract: A pumpdown circuit uses voltage sensing to bring a low node to a potential of V.sub.SS +V.sub.T by first grounding the node and then floating the node to the V.sub.SS +V.sub.T potential. When a sensing node is at the V.sub.SS +V.sub.T potential, the sensing node is maintained at a level above ground by leakage current through a pump-up circuit. Biasing the digit and digit* lines to a potential V.sub.T above ground reduces current (amperage) requirement, because the digit and digit* lines do not have to be discharged completely to ground. The momentary discharge of the sense amp node to ground allows the sense amp to behave like a conventional sense amp during initial sensing, thereby allowing a minimum digit/digit* sensing potential to approximate ground plus V.sub.T.
    Type: Grant
    Filed: September 30, 1988
    Date of Patent: January 30, 1990
    Assignee: Micron Technology, Inc.
    Inventors: Wen-Foo Chern, Ward D. Parkinson, Zhitong Chen, Gary M. Johnson, Tyler A. Lowrey, Thomas M. Trent