Abstract: A data processing system is provided with multiple system clock sources operating at different frequencies for selectively and synchronously driving a plurality of clock pulse generators. The clock pulse generators include four-stage ring counters which may be controlled to produce either four or eight phase clocking signals. When a change is to be made from one system clock source to another, the clock pulse generators are stopped. A phase capture register stores an indication of the last phase generated. While the clock pulse generators are stopped, the change over to the new system clock source is made. The clock pulse generators are restarted at a first time or a second, later time depending upon whether the stored phase indication indicates that the clock pulse generators were stopped at one of phases 5-8 or one of phases 1-4.