Abstract: Embedded packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a semiconductor die is embedded in a dielectric body comprising a dielectric polymer composition characterized by a conductivity transition temperature Tc, a first activation energy EaLow for conduction in a temperature range below Tc, and a second activation energy EaHigh for conduction in a temperature range above Tc. A test methodology is disclosed for selecting a dielectric epoxy composition having values of Tc, EaLow, and EaHigh that provide a conduction value below a required reliability threshold, e.g. ?5×10?13 S/cm, for a specified operating voltage and temperature. For example, the power semiconductor device comprises a GaN HEMT rated for operation at ?100V wherein the package body is formed from a laminated dielectric epoxy composition for operation at >150 C, wherein Tc is ?75 C, EaLow is ?0.

Abstract: A semiconductor device structure for a power transistor structure wherein a drain terminal structure comprises field plates to control and reduce the peak intensity of the channel electric field at the drain terminal. By forming multiple field plates with the existing metallization layers, the generation of hot carriers and impact ionization near the drain can be reduced. For example, in a GaN HEMT, this effect is achieved with two field plates that have different capacitive coupling and overlap with the drain ohmic contact to achieve a reduction in the channel electric field. The use of this drain terminal structure may offer a reduction in increase of Rdson with aging that may be observed in devices after high voltage stress.

Abstract: GaN HEMT device structures and methods of fabrication are provided. A dielectric layer forms a p-dopant diffusion barrier, and low temperature selective growth of p-GaN within a gate slot in the dielectric layer reduces deleterious effects of out-diffusion of p-dopant into the 2DEG channel. A structured AlxGa1-xN barrier layer includes a first thickness having a first Al %, and a second thickness having a second Al %, greater than the first Al %. At least part of the second thickness of the AlxGa1-xN barrier layer in the gate region is removed, before selective growth of p-GaN in the gate region. The first Al % and first thickness are selected to determine the threshold voltage Vth and the second Al % and second thickness are selected to determine the Rdson and dynamic Rdson of the GaN HEMT, so that each may be separately determined to improve device performance, and provide a smaller input FOM (Figure of Merit).

Abstract: GaN HEMT device structures and methods of fabrication are provided. A masking layer forms a p-dopant diffusion barrier and selective growth of p-GaN in the gate region, using low temperature processing, reduces deleterious effects of out-diffusion of p-dopant into the 2DEG channel. A structured AlxGa1-xN barrier layer includes a first thickness having a first Al %, and a second thickness having a second Al %, greater than the first Al %. At least part of the second thickness of the AlxGa1-xN barrier layer in the gate region is removed, before selective growth of p-GaN in the gate region. The first Al % and first thickness are selected to determine the threshold voltage Vth and the second Al % and second thickness are selected to determine the Rdson and dynamic Rdson of the GaN HEMT, so that each may be separately determined to improve device performance, and provide a smaller input FOM (Figure of Merit).

Abstract: Embedded packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a semiconductor die is embedded in a dielectric body comprising a dielectric polymer composition characterized by a conductivity transition temperature Tc, a first activation energy EaLow for conduction in a temperature range below Tc, and a second activation energy EaHigh for conduction in a temperature range above Tc. A test methodology is disclosed for selecting a dielectric epoxy composition having values of Tc, EaLow, and EaHigh that provide a conduction value below a required reliability threshold, e.g. ?5×10?13 S/cm, for a specified operating voltage and temperature. For example, the power semiconductor device comprises a GaN HEMT rated for operation at ?100V wherein the package body is formed from a laminated dielectric epoxy composition for operation at >150 C, wherein Tc is ?75 C, EaLow is ?0.

Abstract: Embedded packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a semiconductor die is embedded in a dielectric body comprising a dielectric polymer composition characterized by a conductivity transition temperature Tc, a first activation energy EaLow for conduction in a temperature range below Tc, and a second activation energy EaHigh for conduction in a temperature range above Tc. A test methodology is disclosed for selecting a dielectric epoxy composition having values of Tc, EaLow and EaHigh that provide a conduction value below a required reliability threshold, e.g. ?5×10?13 S/cm, for a specified operating voltage and temperature. For example, the power semiconductor device comprises a GaN HEMT for operation at >100V wherein the package body is formed from a laminated dielectric epoxy composition for operation at >150 C, wherein Tc is ?75 C, EaLow is ?0.

Abstract: Embedded packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a semiconductor die is embedded in a dielectric body comprising a dielectric polymer composition characterized by a conductivity transition temperature Tc, a first activation energy EaLow for conduction in a temperature range below Tc, and a second activation energy EaHigh for conduction in a temperature range above Tc. A test methodology is disclosed for selecting a dielectric epoxy composition having values of Tc, EaLow and EaHigh that provide a conduction value below a required reliability threshold, e.g. ?5×10?13 S/cm, for a specified operating voltage and temperature. For example, the power semiconductor device comprises a GaN HEMT for operation at >100V wherein the package body is formed from a laminated dielectric epoxy composition for operation at >150 C, wherein Tc is ?75 C, EaLow is ?0.

Abstract: GaN HEMT device structures and methods of fabrication are provided. A masking layer forms a p-dopant diffusion barrier and selective growth of p-GaN in the gate region, using low temperature processing, reduces deleterious effects of out-diffusion of p-dopant into the 2DEG channel. A structured AlxGa1-xN barrier layer includes a first thickness having a first Al %, and a second thickness having a second Al %, greater than the first Al %. At least part of the second thickness of the AlxGa1-xN barrier layer in the gate region is removed, before selective growth of p-GaN in the gate region. The first Al % and first thickness are selected to determine the threshold voltage Vth and the second Al % and second thickness are selected to determine the Rdson and dynamic Rdson of the GaN HEMT, so that each may be separately determined to improve device performance, and provide a smaller input FOM (Figure of Merit).

Abstract: A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and also over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions.

Abstract: A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions.

Abstract: A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions.

Abstract: A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and also over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions.

Abstract: Improved high quality gate dielectrics and methods of preparing such dielectrics are provided. Preferred dielectrics comprise a rare earth doped dielectric such as silicon dioxide or silicon oxynitride. In particular, cerium doped silicon dioxide shows an unexpectedly high charge-to-breakdown QBD, believed to be due to conversion of excess hot electron energy as photons, which reduces deleterious hot electron effects such as creation of traps or other damage. Rare earth doped dielectrics therefore have particular application as gate dielectrics or gate insulators for semiconductor devices such as floating gate MOSFETs, as used in as flash memories, which rely on electron injection and charge transfer and storage.

Abstract: A light emitting device structure, wherein the emitter layer structure comprises one or more device wells defined by thick field oxide regions, and a method of fabrication thereof are provided. Preferably, by defining device well regions after depositing the emitter layer structure, emitter layer structures with reduced topography may be provided, facilitating processing and improving layer to layer uniformity. The method is particularly applicable to multilayer emitter layer structures, e.g. comprising a layer stack of active layer/drift layer pairs. Preferably, active layers comprise a rare earth oxide, or rare earth doped dielectric such as silicon dioxide, silicon nitride, or silicon oxynitride, and respective drift layers comprise a suitable dielectric, preferably silicon dioxide, of an appropriate thickness to control excitation energy. Pixellated light emitting structures, or large area, high brightness emitter layer structures, e.g.

Abstract: An engineered structure of a light emitting device comprises multiple layers of alternating active and buffer materials disposed between AC or DC electrodes, which generate an electric field. The active layers comprise luminescent centers, e.g. group IV semiconductor nanocrystals, in a host matrix, e.g. a wide bandgap semiconductor or dielectric material such as silicon dioxide or silicon nitride. The buffer layers are comprised of a wide bandgap semiconductor or dielectric material, and designed with a thickness, in the direction of an applied electric field, that ensures that electrons passing therethrough picks up enough energy to excite the luminescent centers in the adjacent active layer at an excitation energy to emit light efficiently at a desired wavelength.

Abstract: Electroluminescent (EL) light emitting structures comprises one or more active layers comprising rare earth luminescent centers in a host matrix for emitting light of a particular color or wavelength and electrodes for application of an electric field and current injection for excitation of light emission. The host matrix is preferably a dielectric containing the rare earth luminescent centers, e.g. rare earth doped silicon dioxide, silicon nitride, silicon oxynitrides, alumina, dielectrics of the general formula SiaAlbOcNd, or rare earth oxides. For efficient impact excitation, corresponding drift layers adjacent each active layer have a thickness related to a respective excitation energy of an adjacent active layer. A stack of active layers emitting different colors may be combined to provide white light. For rare earth species having a host dependent emission spectrum, spectral emission of the stack may be tuned by appropriate selection of a different host matrix in successive active layers.

Abstract: Electroluminescent (EL) devices structures are provided comprising a hot electron stopper layer structure to capture hot electrons and dissipate their energy, thereby reducing damage to the transparent conducting oxide (TCO) layer and reducing other hot electron effects, such as charging effects, which impact reliability of EL device structures. The stopper layer structure may comprise a single layer or multiple layers provided between the TCO electrode layer and the emitter structure, and may also function to reduce diffusion or chemical interactions between the TCO and the emitter layer structure. Optionally, stopper layers may also be provided within the emitter structure. Suitable stopper layer materials are wideband gap semiconductors or dielectrics, preferably transparent at wavelengths emitted by the EL device characterized by high impact ionization rates, and/or high relative permittivity relative to adjacent layers of the emitter structure.

Abstract: A light emitting device includes an active layer structure, which has one or more active layers with luminescent centers, e.g. a wide bandgap material with semiconductor nano-particles, deposited on a substrate. For the practical extraction of light from the active layer structure, a transparent electrode is disposed over the active layer structure and a base electrode is placed under the substrate. Transition layers, having a higher conductivity than a top layer of the active layer structure, are formed at contact regions between the upper transparent electrode and the active layer structure, and between the active layer structure and the substrate. Accordingly the high field regions associated with the active layer structure are moved back and away from contact regions, thereby reducing the electric field necessary to generate a desired current to flow between the transparent electrode, the active layer structure and the substrate, and reducing associated deleterious effects of larger electric fields.

Abstract: Improved high quality gate dielectrics and methods of preparing such dielectrics are provided. Preferred dielectrics comprise a rare earth doped dielectric such as silicon dioxide or silicon oxynitride. In particular, cerium doped silicon dioxide shows an unexpectedly high charge-to-breakdown QBD, believed to be due to conversion of excess hot electron energy as photons, which reduces deleterious hot electron effects such as creation of traps or other damage. Rare earth doped dielectrics therefore have particular application as gate dielectrics or gate insulators for semiconductor devices such as floating gate MOSFETs, as used in as flash memories, which rely on electron injection and charge transfer and storage.

Abstract: A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and also over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions.