Patents by Inventor Thomas Madaelil

Thomas Madaelil has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods, systems, and apparatuses for out-of-order access to a shared microcode sequencer by a clustered decode pipeline
    Patent number: 11907712
    Abstract: Systems, methods, and apparatuses relating to circuitry to implement out-of-order access to a shared microcode sequencer by a clustered decode pipeline are described.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: February 20, 2024
    Assignee: Intel Corporation
    Inventors: Thomas Madaelil, Jonathan Combs, Vikash Agarwal
  • METHODS, SYSTEMS, AND APPARATUSES FOR OUT-OF-ORDER ACCESS TO A SHARED MICROCODE SEQUENCER BY A CLUSTERED DECODE PIPELINE
    Publication number: 20220100500
    Abstract: Systems, methods, and apparatuses relating to circuitry to implement out-of-order access to a shared microcode sequencer by a clustered decode pipeline are described.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 31, 2022
    Inventors: Thomas MADAELIL, Jonathan COMBS, Vikash AGARWAL
  • CIRCUITRY AND METHODS FOR POWER EFFICIENT GENERATION OF LENGTH MARKERS FOR A VARIABLE LENGTH INSTRUCTION SET
    Publication number: 20220100516
    Abstract: Systems, methods, and apparatuses for power efficient generation of length markers for a variable length instruction set are described.
    Type: Application
    Filed: September 26, 2020
    Publication date: March 31, 2022
    Inventors: Thomas MADAELIL, Jonathan COMBS, Khary ALEXANDER, Martin LICHT, Vikash AGARWAL
  • Configurable computer system
    Publication number: 20080114918
    Abstract: A method for providing multiple configurations for a computer system. The method provides interconnection of processor boards in a first configuration and a second configuration. In the first configuration, a first plurality of processor boards are interconnected through a first backplane. In a second configuration, a second plurality of processor boards are interconnected through a second backplane. The first and second pluralities of processor boards are interchangeable with each other.
    Type: Application
    Filed: November 9, 2006
    Publication date: May 15, 2008
    Inventors: Ravi B. Bingi, Ranger H. Lam, Thomas Madaelil, Lloyd W. Gauthier, Brian E. Longhenry, Kristy M. Cates, Christopher E. Tressler