Abstract: A serial interface controller provides for transferring data between a data source having a least one channel and a processor. The serial interface controller has a plurality of control registers; the control registers in turn include a data structure for configuring the serial interface controller for a data transfer. That data structure further comprises a field for selectively setting the serial interface controller in its run mode or its configuration mode; a field for storing the I/O mode of the serial interface controller; a field for storing the address of the active data channel; and, a field for storing the system clock rate.

Abstract: A serial interface controller provides for transferring data between a data source having a least one channel and a processor. The serial interface controller has a plurality of control registers; the control registers in turn include a data structure for configuring the serial interface controller for a data transfer. That data structure further comprises a field for selectively setting the serial interface controller in its run mode or its configuration mode; a field for storing the I/O mode of the serial interface controller; a field for storing the address of the active data channel; and, a field for storing the system clock rate.

Abstract: An integrated circuit for implementing a digital filter has a data memory; the data memory having two ports to permit the access of two data samples at the same time, and a coefficient memory for storing filter coefficients. A first adder adds data samples from first and second data memory ports; a multiplier multiplies a value from the first adder by a value from the coefficient memory; and, a second adder accumulates values from the multiplier. A master controller is provided configured for selectively storing the accumulated values in the data memory for further processing or outputting the accumulated values. An address and control block communicating with the data memory and the coefficient memory holds values appropriate to the filter to be executed. The address and control block has two sets of a first set of registers for holding values for a first pre-determined digital filter and a second pre-determined digital filter in cascade.