Abstract: A cutting tool has a tool body with a proximal end for mounting to drive unit and a distal end for engaging a workpiece for cutting. The tool body extends longitudinally along a central axis of the tool body. The tool body defines an interior space therein. One or more additively manufactured passive dampers are disposed in the interior space of the tool body.

Abstract: Described herein are improved techniques for measuring propagation delay of an integrated circuit that facilitate performing propagation delay measurements on-chip. Some embodiments relate to an integrated circuit comprising programmable oscillator circuitry with a plurality of oscillator stages that are switchable into and out of a delay path based on control signals from a controller, allowing the same programmable oscillator to generate many different oscillator signals according to the received control signals, for the controller to determine a central tendency and/or variance of propagation delay of the integrated circuit. Some embodiments relate to an integrated circuit including programmable delay paths configured to provide an amount of cell delay and an amount of wire delay based on control signals from a controller, allowing the same programmable delay path to generate signals for measuring delays due to cell and wire delays of the integrated circuit.

Abstract: Described herein are improved techniques for measuring propagation delay of an integrated circuit that facilitate performing propagation delay measurements on-chip. Some embodiments relate to an integrated circuit comprising programmable oscillator circuitry with a plurality of oscillator stages that are switchable into and out of a delay path based on control signals from a controller, allowing the same programmable oscillator to generate many different oscillator signals according to the received control signals, for the controller to determine a central tendency and/or variance of propagation delay of the integrated circuit. Some embodiments relate to an integrated circuit including programmable delay paths configured to provide an amount of cell delay and an amount of wire delay based on control signals from a controller, allowing the same programmable delay path to generate signals for measuring delays due to cell and wire delays of the integrated circuit.

Abstract: An integrated circuit includes a programmable delay path comprising a plurality of path delay tuners configured to receive a plurality of control signals and add to the programmable delay path an amount of cell delay and an amount of wire delay that are based on the plurality of control signals. The integrated circuit further includes a controller configured to provide the plurality of control signals to the programmable delay path, receive a signal from the programmable delay path, and compare the signal to a reference signal.

Abstract: Described herein are improved techniques for measuring propagation delay of an integrated circuit that facilitate performing propagation delay measurements on-chip. Some embodiments relate to an integrated circuit comprising programmable oscillator circuitry with a plurality of oscillator stages that are switchable into and out of a delay path based on control signals from a controller, allowing the same programmable oscillator to generate many different oscillator signals according to the received control signals, for the controller to determine a central tendency and/or variance of propagation delay of the integrated circuit. Some embodiments relate to an integrated circuit including programmable delay paths configured to provide an amount of cell delay and an amount of wire delay based on control signals from a controller, allowing the same programmable delay path to generate signals for measuring delays due to cell and wire delays of the integrated circuit.

Abstract: Clock circuits designed to compensate for supply voltage fluctuations (e.g., supply voltage droops) in central processing units (CPUs) are described. The clock circuits described herein involve reducing the clock frequency in response to a decrease to the supply voltage to a value that is approximately equal (or below) to the maximum operating frequency of the CPU at that particular supply voltage. The clock circuits described herein may include a frequency locked loops (FLL). Such FLLs may be designed to lock to a reference frequency when the supply voltage is approximately constant and to deviate from the reference frequency in response to variations in the supply voltage. In some embodiments, an FLL operates in the same supply voltage domain as the CPU.

Abstract: Described herein are improved techniques for measuring propagation delay of an integrated circuit that facilitate performing propagation delay measurements on-chip. Some embodiments relate to an integrated circuit comprising programmable oscillator circuitry with a plurality of oscillator stages that are switchable into and out of a delay path based on control signals from a controller, allowing the same programmable oscillator to generate many different oscillator signals according to the received control signals, for the controller to determine a central tendency and/or variance of propagation delay of the integrated circuit. Some embodiments relate to an integrated circuit including programmable delay paths configured to provide an amount of cell delay and an amount of wire delay based on control signals from a controller, allowing the same programmable delay path to generate signals for measuring delays due to cell and wire delays of the integrated circuit.

Abstract: Clock circuits designed to compensate for supply voltage fluctuations (e.g., supply voltage droops) in central processing units (CPUs) are described. The clock circuits described herein involve reducing the clock frequency in response to a decrease to the supply voltage to a value that is approximately equal (or below) to the maximum operating frequency of the CPU at that particular supply voltage. The clock circuits described herein may include a frequency locked loops (FLL). Such FLLs may be designed to lock to a reference frequency when the supply voltage is approximately constant and to deviate from the reference frequency in response to variations in the supply voltage. In some embodiments, an FLL operates in the same supply voltage domain as the CPU.

Abstract: Various examples with respect to dual threshold clock control are described. A method involves sensing an input voltage of a processing circuit with a first mechanism and a second mechanism different from the first mechanism. The method also involves regulating a first droop of the input voltage using the first mechanism. The method further involves regulating a subsequent droop of the input voltage after the first droop using the second mechanism.

Abstract: A vehicle includes a front end assembly including a headlamp assembly. The headlamp assembly includes a housing that defines a cavity and an outer lens that closes the cavity. A low beam headlamp assembly is located within the cavity. A shared cover lens is located within the cavity. The shared cover lens has an illumination region. A first light guide device directs a beam of light at the illumination region. A second light guide device directs a beam of light at an area offset from the illumination region and also at the illumination region.

Abstract: A standard cell circuit includes a standard cell unit and a first resistive device. The standard cell unit is coupled to at least one resistor. The first resistive device is coupled to the standard cell unit and provides a first current path for a first current to flow through.

Abstract: A dynamic power meter circuit receives a set of clock signals. The clock signals are summed by a clock sum adder, thereby generating a clock sum value. A dynamic power meter output value is generated based at least in part on the clock sum value. In one particular example, a dynamic power meter circuit receives clock signals and from them generates a clock sum model sub-value. The dynamic power meter circuit also receives event signals, and from them generates an architectural event model sub-value. A corresponding pair of clock sum model sub-value and architectural event model sub-value are then ratiometrically combined, thereby generating a dynamic power meter output value. Due to the use of both event signals and clock signals, a stream of dynamic power meter output values is generated that more closely tracks actual dynamic power of a circuit being monitored.

Abstract: A vehicle includes a front end assembly including a headlamp assembly. The headlamp assembly includes a housing that defines a cavity and an outer lens that closes the cavity. A low beam headlamp assembly is located within the cavity. A shared cover lens is located within the cavity. The shared cover lens has an illumination region. A first light guide device directs a beam of light at the illumination region. A second light guide device directs a beam of light at an area offset from the illumination region and also at the illumination region.

Abstract: An apparatus, a lighting apparatus, and a vehicle with an interlocking joint are described. The interlocking joint includes a first part made of a first material including a plurality of grooves, and a second part molded over the plurality of the grooves of the first part creating a mechanical bond and a chemical bond between the first part and the second part.

Abstract: A method of detecting and preventing over current induced system failure is provided. An OC protect controller monitors a CPU total power consumption based on received CPU activity information. In response to the monitoring, if the CPU power consumption is over a threshold, then the OC protect controller outputs a frequency dithering control signal to reduce the CPU clock frequency such that the CPU does not reach an OC limit. The OC protect controller also outputs a PLL frequency control signal to reduce the PLL clock frequency to improve system efficiency.

Abstract: A lighting device including a reflector having a plurality of reflex pins, a light pipe integrally connected to the reflector along the periphery of the reflector forming a neck between the light pipe and the reflector, wherein the light pipe and the reflector function independently, and a light source connected to the light pipe.

Abstract: A processing device performs dual-rail power equalization for its memory cell array and logic circuitry. The memory cell array is coupled to a first power rail through a first switch to receive a first voltage level. The logic circuitry is coupled to a second power rail through a second switch to receive a second voltage level that is different from the first voltage level. The processing device also includes a power switch coupled to at least the second power rail and operative to be enabled to equalize voltage supplied to the memory cell array and the logic circuitry.

Abstract: The present disclosure describes a fin plug assembly for removably mounting a watercraft fin on a watercraft. In some embodiments the fin plug assembly includes a fin plug, a fin plug finishing insert and in some instances, a shelf-like support that is configured to house the fin plug assembly. Methods of making, methods of installing, and tools for installing the fin plug assembly in a watercraft are also described.

Abstract: A control method for a clock signal for a CPU contained in a CMOS circuit includes: when a load current for the CMOS circuit is enabled, generating a first clock signal; in a first period, selectively gating certain cycles of the first clock signal to generate a second clock signal which has a clock rate less than a clock rate of the first clock signal; and in a second period, dithering in the gated cycles to increase the clock rate of the second clock signal to be equal to that of the first clock signal. The second clock signal is continuously input to the CMOS circuit during the first period and the second period.

Abstract: A method of detecting and preventing over current induced system failure is provided. An OC protect controller monitors a CPU total power consumption based on received CPU activity information. In response to the monitoring, if the CPU power consumption is over a threshold, then the OC protect controller outputs a frequency dithering control signal to reduce the CPU clock frequency such that the CPU does not reach an OC limit. The OC protect controller also outputs a PLL frequency control signal to reduce the PLL clock frequency to improve system efficiency.