Abstract: A sense amplifier circuit for sensing a data state of a data cell during a read cycle is described. The circuit includes a first stage with first circuitry to output a reference voltage and a data voltage relating to the data state of the data cell. The circuit further includes a second stage with circuitry to amplify a difference between the reference voltage and the data voltage. This circuitry includes a plurality of inverters and a plurality of capacitors. The read cycle includes a compensation phase. During the compensation phase the circuitry stores, at the capacitors, a voltage difference caused by a device mismatch of the inverters. After the compensation phase the circuitry amplifies the difference between the reference voltage and the data voltage, and compensates for the device mismatch using the stored voltage difference at the capacitors.

Abstract: A magnetoresistive random access memory (MRAM) system is described. The system includes a sense amplifier circuit for sensing a data state of an MRAM data cell. The circuit includes a first leg and a second leg, and is configured to perform a two-phase read including a first phase in which a first transistor is coupled to a reference resistance circuitry and a second transistor is coupled to a data resistance circuitry, and a second phase in which the first transistor is coupled to the data resistance circuitry and the second transistor is coupled to the reference resistance circuitry. The circuit further includes a reference trim circuitry and a data trim circuitry configured to correct for device mismatch errors relating to the two-phase read of the sense amplifier circuit. The circuit further includes a comparator circuit configured to output the data state of the data cell.

Abstract: A magnetoresistive random access memory (MRAM) system is described. The system includes a sense amplifier that performs a two-phase read, including a first phase in which a first n-channel transistor is coupled to a reference resistance and a second n-channel transistor is coupled to a data resistance, and a second phase in which the first n-channel transistor is coupled to the data resistance and the second n-channel transistor is coupled to the reference resistance. The circuit further includes a first active amplifier for controlling a gate voltage of the first n-channel transistor and a second active amplifier for controlling a gate voltage of the second n-channel transistor. The circuit further includes a comparator configured to output the data state of the cell based on input of a first voltage related to a reference resistance and a second voltage related to a data resistance.

Abstract: A digital circuit and a method for operating the same. The digital circuit includes (a) M×N regular cells electrically arranged in M rows and N columns, (b) N reference cells corresponding one-to-one to the N columns, and (c) N comparing circuits corresponding one-to-one to the N columns. Each regular cell is electrically coupled to a comparing circuit. Each reference cell is electrically coupled to the associated comparing circuit. Each regular cell includes a first tap node. Each reference cell includes P tap nodes. If a first voltage of the first tap node of a regular cell is between two voltages of two tap nodes of the P tap nodes of the associated reference cell, then the associated comparing circuit is capable of generating a first signal. If the first voltage is not between the two voltages, then the associated comparing circuit is capable of generating a second signal.

Abstract: A method of, and a circuit for, measuring a capacitor gate dielectric thickness. The method includes the step of providing a circuit including a gate dielectric capacitor, and charging the circuit with a known current. A voltage output from said circuit is measured, and this voltage is proportional to the gate dielectric capacitor thickness. The present invention may be effectively employed to obtain a number of important advantages. First, because the supply voltage scales with gate dielectric thickness, chip performance is maximized, even when gate oxide runs thick. Furthermore, oxide reliability is not affected because a constant electric field is guaranteed.

Abstract: A method of, and a circuit for, measuring a capacitor gate dielectric thickness. The method comprises the step of providing a circuit including a gate dielectric capacitor, and charging the circuit with a known current. A voltage output from said circuit is measured, and this voltage is proportional to the gate dielectric capacitor thickness. The present invention may be effectively employed to obtain a number of important advantages. First, because the supply voltage scales with gate dielectric thickness, chip performance is maximized, even when gate oxide runs thick. Furthermore, oxide reliability is not affected because a constant electric field is guaranteed.

Abstract: An OCD (off chip driver) to be used in either a mixed power supply (i.e. three and five volts) environment, without causing damaging stress to the circuitry, or in a single power supply environment (three volts). The OCD has sequential circuitry to control the slew rate of the current leaving the chip. By providing three output driver circuits, the logic states can control the slew rate (dl/dt) of the current and thus control the switching speed between a logical one and zero. Additionally, with this circuitry, the control logic on the gates of pull up PFETs, the low voltage on the gates will be above a certain level, for example 0.5 volts at the gates that eliminates the PFET's stresses due to the OCD operation in an external 5 volt environment. Furthermore, the logic circuitry is designed to have no direct current penalties; there is no draw of any direct current.