Patents by Inventor Thomas Massingill

Thomas Massingill has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Cavity down semiconductor package
    Publication number: 20050218514
    Abstract: A semiconductor package is disclosed for an integrated circuit die (52). The integrated circuit die is electrically connected to the package substrate by either die solder balls (53a), or wirebonds (53b). The package substrate (50), a single sided printed wiring board, has a thick metal core (100), consisting of a base metal, a core capacitor, and one or more thin build up layers.
    Type: Application
    Filed: April 1, 2005
    Publication date: October 6, 2005
    Inventor: Thomas Massingill
  • Semiconductor with polymeric layer
    Patent number: 6271107
    Abstract: Bumped semiconductor substrates and methods for forming bumped semiconductor substrates are disclosed. The bumped semiconductor substrates have a polymeric layer, which can serve as a passivation layer for chips derived from the semiconductor substrate.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: August 7, 2001
    Assignee: Fujitsu Limited
    Inventors: Thomas Massingill, Mark Thomas McCormack, Hunt Hang Jiang
  • Multilayer laminated substrates with high density interconnects and methods of making the same
    Patent number: 6163957
    Abstract: Multilayer circuit lamination methods and circuit layer structures are disclosed which enable one to manufacture high-density multichip module boards and the like at lower cost, with higher yield, with higher signal densities, and with fewer processing steps.
    Type: Grant
    Filed: November 13, 1998
    Date of Patent: December 26, 2000
    Assignee: Fujitsu Limited
    Inventors: Hunt Hang Jiang, Thomas Massingill, Mark Thomas McCormack, Michael Guang-Tzong Lee