Abstract: A low power bus hold circuit includes: a first inverter having an input coupled to a bus hold input node; and a second inverter having a first input coupled to a first output of the first inverter and a second input coupled to a second output of the first inverter, wherein the first and second outputs of the first inverter are separated by a resistor, and having an output coupled to the bus hold input node.

Abstract: A method for enabling access to a resource shared by at least two processors over a bus that supports an atomic instruction, wherein a first processor does not support the atomic instruction, the method comprising the steps of providing an atomic instruction emulator coupled to the bus, the atomic instruction emulator including at least two register sets for implementing an atomic instruction; receiving by the emulator over the bus an emulation request from the first processor to perform the atomic instruction on the shared resource, the request including an address location; and performing by the emulator the atomic instruction for the processor using the data and the address location from the request.

Abstract: A heterogeneous integrated circuit having a digital signal processor and at least one programmable logic core. An AMBA AHB couples the cores and most other functional units on the IC. The PLCs are also coupled to the DSP through a separate DMA sharing unit to the DSP, and particularly to the DSP memory. The memory sharing arrangement provides a separate high-speed data transfer mechanism between the PLCs and the DSP. Memory sharing is controlled to allocate the full bandwidth of the DSP memory to the PLCs and other DMA devices in proportion to their operating speeds. The AMBA AHB allows the DSP to control the PLC operations without interference with high-speed data transfers.

Abstract: A method for enabling access to a resource shared by at least two processors over a bus that supports an atomic instruction, wherein a first processor does not support the atomic instruction, the method comprising the steps of providing an atomic instruction emulator coupled to the bus, the atomic instruction emulator including at least two register sets for implementing an atomic instruction; receiving by the emulator over the bus an emulation request from the first processor to perform the atomic instruction on the shared resource, the request including an address location; and performing by the emulator the atomic instruction for the processor using the data and the address location from the request.

Abstract: A heterogeneous integrated circuit having a digital signal processor and at least one programmable logic core. An AMBA AHB couples the cores and most other functional units on the IC. The PLCs are also coupled to the DSP through a separate DMA sharing unit to the DSP, and particularly to the DSP memory. The memory sharing arrangement provides a separate high-speed data transfer mechanism between the PLCs and the DSP. The AMBA AHB allows the DSP to control the PLC operations without interference with high-speed data transfers.

Abstract: A heterogeneous integrated circuit having a digital signal processor and two programmable logic cores, PLCs. An AMBA AHB couples the cores and most other functional units on the IC. The PLCs are also coupled to the DSP through a separate DMA sharing unit to the DSP, and particularly to the DSP memory. The memory sharing arrangement provides a separate high-speed data transfer mechanism between the PLCs and the DSP. The AMBA AHB allows the DSP to control the PLC operations without interference with high-speed data transfers. The DSP may reconfigure one PLC using the AMBA AHB, while it is processing data with the other PLC.

Abstract: A heterogeneous integrated circuit having a digital signal processor and at least one programmable logic core. An AMBA AHB couples the cores and most other functional units on the IC. The PLCs are also coupled to the DSP through a separate DMA sharing unit to the DSP, and particularly to the DSP memory. The memory sharing arrangement provides a separate high-speed data transfer mechanism between the PLCs and the DSP. Memory sharing is controlled to allocate the full bandwidth of the DSP memory to the PLCs and other DMA devices in proportion to their operating speeds. The AMBA AHB allows the DSP to control the PLC operations without interference with high-speed data transfers.

Abstract: A heterogeneous integrated circuit having a digital signal processor and at least one programmable logic core. An AMBA AHB couples the cores and most other functional units on the IC. The PLCs are also coupled to the DSP through a separate DMA sharing unit to the DSP, and particularly to the DSP memory. The memory sharing arrangement provides a separate high-speed data transfer mechanism between the PLCs and the DSP. The AMBA AHB allows the DSP to control the PLC operations without interference with high-speed data transfers.

Abstract: A heterogeneous integrated circuit having a digital signal processor and two programmable logic cores, PLCs. An AMBA AHB couples the cores and most other functional units on the IC. The PLCs are also coupled to the DSP through a separate DMA sharing unit to the DSP, and particularly to the DSP memory. The memory sharing arrangement provides a separate high-speed data transfer mechanism between the PLCs and the DSP. The AMBA AHB allows the DSP to control the PLC operations without interference with high-speed data transfers. The DSP may reconfigure one PLC using the AMBA AHB, while it is processing data with the other PLC.