Abstract: Automatic power saving for decreasing power demand during a power interruption while maintaining the appearance of full operation of a signal processor including predefined power consuming circuits, a communications interface, and a state machine includes sensing when a power supply interruption has occurred, providing a clock signal, halting the clock signal to the predefined power consuming circuits during a power interruption; and continuing to provide a clock signal to a communications interface regardless of a sensed interruption for maintaining the appearance of normal operations during the sensed interruption.

Abstract: A circuit die to circuit die interface system includes a first circuit die with a first circuit having a first default signal, at least a second circuit die with a second circuit having a second default signal; and a logic circuit disposed on one of the first and second circuit dies and enabled by a default signal from all but one of the circuits to transmit a communication signal from the remaining circuit.

Abstract: An input biasing system for accommodating a floating power supply to the range of an input signal includes input terminals for receiving a input signal and a biasing circuit including a first impedance connected between one of the input terminals and a floating power supply and a second impedance connected between another of the input terminals and the ground of the floating power supply for bracketing the floating power supply about the input signal.

Abstract: A reduced chop rate analog to digital converter technique including selectively weighting input samples to a digital filter, alternately inverting the polarity of an input error into positive and negative error components; and generating the positive and negative error components in a plurality of time response intervals of the digital filter in which the sum of the weights of the positive and negative error components are substantially equal.

Abstract: A circuit used for testing an integrated circuit including a chop circuit. A source of a test signal coupled to a first pair of pins of the integrated circuit. A test signal measuring device to measure the test signal coupled to a second pair of pins of the integrated circuit. A chop circuit controller produces a control signal and for feeding such control to the chop circuit and the test signal measuring device. In response to the control signal, the chop circuit couples the first pair of pins to the second pair of pins with a first polarity during a first period of time and couples the first pair of pins to the second pair of pins with an opposite polarity during a second period of time.